Fabricating method for a semiconductor device comprising gate oxide layers of various thicknesses

• US 6,265,267 B1
• Filed: 11/04/1999
• Issued: 07/24/2001
• Est. Priority Date: 11/04/1999
• Status: Expired due to Term

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Huang, Chih-Jen
• Primary Examiner(s): BOOTH, RICHARD A
• Application Number:
  US09/434,033
• Time in Patent Office: 628 Days
• Field of Search: 438/257-267, 438/981, 438/770
• US Class Current: 438/258
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/49 comprising different types of peripheral transistor
• CPC Class Codes: Y10S 438/981 Utilizing varying dielectric thickness

Abstract

A method of fabricating a semiconductor device with various thicknesses of the gate oxide layers is described, which method is applicable to a substrate having a first region and a second region, wherein the first region has a first conductive layer to isolate the first gate oxide layer from the substrate. Thereafter, a first oxide layer/nitride layer is formed on the first conductive layer, followed by forming a doped polysilicon layer on the first oxide layer/nitride layer, wherein the doped polysilicon layer is not formed in the second region. Subsequently, a second gate oxide layer is formed on the substrate of the second region, whereas a first oxide layer/nitride layer/second oxide layer is concurrently converted from the oxide layer/nitride layer/doped polysilicon layer. A defined second conductive layer is then formed on the first oxide layer/nitride layer/second oxide layer and the second gate oxide layer.

Claims

1. A fabrication method for a semiconductor device comprising various thicknesses of oxide layers, which is applicable to a substrate comprising a first region and a second region, the method comprising the steps of:

forming a first oxide layer on the substrate;

forming a doped polysilicon layer on the first oxide layer;

removing the first oxide layer and the doped polysilicon layer in the first region to expose the substrate of the first region;

forming a second oxide layer on the substrate in the first region;

oxidizing the doped polysilicon layer to a poly-oxide layer; and

removing the poly-oxide layer to expose the first oxide layer, wherein the first oxide layer is thicker than the second oxide layer.

2. The fabrication method for a semiconductor device comprising various thicknesses of oxide layers according to claim 1, wherein photolithography and etching are further conducted to remove the doped polysilicon layer and the first oxide layer in the first region.

3. The fabrication method for a semiconductor device comprising various thicknesses of oxide layers according to claim 1, wherein the formation of the second oxide layer includes conducting a thermal process.

4. The fabrication method for a semiconductor device comprising various thicknesses of oxide layers according to claim 3, wherein the formation of the poly-oxide layer from the doped polysilicon layer occurs concurrently with the thermal process.

5. The fabrication method for a semiconductor device comprising various thicknesses of oxide layers according to claim 1, wherein the poly-oxide layer is removed by wet etching.

6. The fabrication method for a semiconductor device comprising various thicknesses of oxide layers according to claim 1, wherein the step of wet etching includes using an etchant with a sufficiently high etching selectivity ratio to remove the poly-oxide layer without removing the first oxide layer or the second oxide layer.