High temperature oxide deposition process for fabricating an ONO floating-gate electrode in a two bit EEPROM device

• US 6,265,268 B1
• Filed: 10/25/1999
• Issued: 07/24/2001
• Est. Priority Date: 10/25/1999
• Status: Expired due to Term

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Advanced Micro Devices, Inc., Fujitsu Limited
• Inventors: Halliyal, Arvind, Ogle, Robert B., Komori, Hideki, Au, Kenneth
• Primary Examiner(s): BOOTH, RICHARD A
• Application Number:
  US09/426,672
• Time in Patent Office: 638 Days
• Field of Search: 438/261, 438/265, 438/287, 438/257-267
• US Class Current: 438/261
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/7923 Programmable transistors with more than two possible different levels of programmation

Abstract

A process for fabricating an ONO floating-gate electrode in a two-bit EEPROM device includes the formation of a top oxide layer using a high-temperature-oxide (HTO) deposition process in which the HTO process is carried out at a temperature of about 700 to about 800° C. by either an LPCVD or RTCVD deposition processor. The process further includes the sequential formation of a silicon nitride layer and a top oxide layer using an in-situ LPCVD or RTCVD deposition process in which the silicon nitride layer is not exposed to ambient atmosphere prior to the formation of the top oxide layer. The formation of the top oxide layer using an HTO deposition process provides an improved two-bit EEPROM memory device by reducing charge leakage in the ONO floating-gate electrode.

Claims

1. A process for fabricating an ONO floating-gate electrode in a two-bit EEPROM device comprising the steps of:

providing a semiconductor substrate;

thermally growing a first silicon oxide layer overlying the semiconductor substrate;

forming a silicon nitride layer overlying the first silicon oxide layer; and

maintaining at least two charge isolation regions in the silicon nitride layer by depositing a second layer of silicon oxide overlying the silicon nitride layer using a high temperature oxide deposition process,

wherein the high temperature oxide deposition process is carried out at a temperature of about 700 to about 800°

C.

2. The process of claim 1, wherein the step of depositing a second oxide layer comprises low pressure chemical vapor deposition using nitrous oxide and a second gas selected from the group consisting of silane and dichlorosilane.

3. The process of claim 2, wherein the step of depositing a second oxide layer comprises low pressure chemical vapor deposition using about 0.5 to about 2 slpm nitrous oxide and about 10 to about 50 sccm of the second gas.

4. The process of claim 1 , wherein the step of depositing a second oxide layer comprises rapid thermal chemical vapor deposition using nitrous oxide and dichlorosilane.

5. The process of claim 4, wherein the step of depositing a second oxide layer comprises rapid thermal chemical vapor deposition using about 1 to about 3 slpm nitrous oxide and about 25 to about 75 sccm dichlorosilane to form a silicon oxide layer having a thickness of about 50 to about 150 angstroms.

6. The process of claim 1, wherein the step of depositing a silicon nitride layer comprises rapid thermal chemical vapor deposition using about 0.5 to 2 slpm ammonia and about 20 to about 50 sccm of a second gas selected from the group consisting of silane and dichlorosilane.

7. The process of claim 1, wherein the step of forming a silicon nitride layer and the step of depositing a second silicon oxide layer comprises a process selected from the group consisting of RTCVD and LPCVD, wherein the both the silicon nitride layer and the second silicon oxide layer are sequentially formed in a processing apparatus in the absence exposure to ambient atmosphere.

8. A process for fabricating a stacked-gate structure including an ONO floating-gate electrode in a two-bit EEPROM device comprising the steps of:

providing a semiconductor substrate having a first bit-line oxide layer and a second bit-line oxide layer therein separated by a substrate surface region;

forming an ONO layer on the substrate surface region by first, thermally growing a first silicon oxide layer on the substrate surface region, second, forming a silicon nitride layer overlying the first silicon oxide layer; and

third, maintaining at least two charge isolation regions in the silicon nitride layer by depositing a second layer of silicon oxide overlying the silicon nitride layer using a high temperature oxide deposition process,

wherein the high temperature oxide deposition process is carried out at a temperature of about 700 to about 800°

C.;

depositing a gate electrode layer overlying the ONO layer; and

forming a stacked-gate structure on the substrate surface region,

wherein the stacked-gate structure includes a control-gate electrode overlying an ONO floating-gate electrode.

9. The process of claim 8, wherein the step of depositing a second oxide layer comprises low pressure chemical vapor deposition using nitrous oxide and a second gas selected from the group consisting of silane and dichlorosilane.

10. The process of claim 9, wherein the step of depositing a second oxide layer comprises low-pressure-chemical-vapor-deposition using about 0.5 to about 2 slpm nitrous oxide and about 10 to about 50 slpm of the second gas.

11. The process of claim 8, wherein the step of depositing a second oxide layer comprises rapid thermal chemical vapor deposition using nitrous oxide and dichlorosilane.

12. The process of claim 11, wherein the step of depositing a second oxide layer comprises rapid thermal chemical vapor deposition using about 1 to about 3 slpm nitrous oxide and about 25 to about 75 sccm dichlorosilane to form a silicon oxide layer having a thickness of about 50 to about 150 angstroms.

13. The process of claim 8, wherein the step of depositing a silicon nitride layer comprises rapid-thermal-chemical-vapor-deposition using about 1 slpm ammonia and about 30 to about 50 sccm of a second gas selected from the group consisting of silane and dichlorosilane.

14. The process of claim 8, wherein the step of forming a silicon nitride layer and the step of depositing a second silicon oxide layer comprises a process selected from the group consisting of RTCVD and LPCVD, wherein the both the silicon nitride layer and the second silicon oxide layer are sequentially formed in a processing apparatus in the absence exposure to ambient atmosphere.

15. A process for fabricating an ONO floating-gate electrode in a two-bit EEPROM device comprising the steps of:

providing a semiconductor substrate having a silicon surface region;

thermally growing a silicon oxide layer overlying the surface region; and

depositing a silicon nitride layer overlying the silicon oxide layer and a top silicon oxide layer using a deposition process selected from the group consisting of RTCVD and LPCVD;

wherein at least two charge isolation regions are maintained in the silicon nitride layer by carrying out the silicon nitride layer and the top silicon oxide layer are sequentially deposited in the absence of exposure to ambient atmosphere; and

wherein the deposition process is carried out at a temperature of about 700 to about 800°

C.

16. The process of claim 15, wherein the step of depositing a second oxide layer comprises an RTCVD process using about 1 to about 3 slpm nitrous oxide and about 25 to about 75 sccm dichlorosilane to form a silicon oxide layer having a thickness of about 50 to about 150 angstroms.

17. The process of claim 16, wherein the RTCVD process comprises a three step sequence including a temperature ramp up step, a deposition step of about 1 minute, and a cool down step.

18. The process of claim 17, wherein the step of depositing a silicon nitride layer using an RTCVD process comprises using about 1 slpm ammonia and about 30 to about 50 sccm of a second gas selected from the group consisting of silane and dichlorosilane.

19. The process of claim 18, wherein the RTCVD process comprises a three step sequence including a temperature ramp up step, a deposition step of about 2 minutes, and a cool down step.

20. The process of claim 19, wherein the RTCVD process forms the silicon nitride layer to a thickness of about 50 to about 150 angstroms and the top silicon oxide layer to a thickness of about 50 to about 150 angstrons.

21. The process of claim 15, wherein the deposition process comprises LPCVD using a batch-type furnace.