Method for fabricating a concave bottom oxide in a trench

• US 6,265,269 B1
• Filed: 08/06/1999
• Issued: 07/24/2001
• Est. Priority Date: 08/04/1999
• Status: Expired due to Term

• Current Assignee: ProMOS Technologies, Inc.
• Original Assignee: Mosel Vitelic Incorporated
• Inventors: Chen, Chien-Hung, Chen, Juinn-Sheng, Lin, Ching-Shun, Wu, Chih-Ta
• Primary Examiner(s): Bowers, Charles
• Assistant Examiner(s): Smoot, Stephen W.
• Application Number:
  US09/369,266
• Time in Patent Office: 718 Days
• Field of Search: 438/268, 438/270, 438/282, 438/197, 438/200, 438/133, 438/138, 438/778, 438/788
• US Class Current: 438/270
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A method for forming a concave bottom oxide layer in a trench, comprising: providing a semiconductor substrate; forming a pad oxide layer on the semiconductor substrate; forming a silicon nitride layer on the pad oxide layer; etching the silicon nitride layer, the pad oxide layer and the semiconductor substrate to form the trench in the semiconductor substrate; depositing a silicon oxide layer to refill into the trench and cover on the silicon nitride layer, wherein the silicon oxide layer has overhang portions at corners of the trench; anisotropically etching the silicon oxide layer to form a concave bottom oxide layer in the trench; etching the silicon oxide layer to remove the silicon oxide layer on the silicon nitride layer and the sidewalls of the trench; removing the silicon nitride layer and the pad oxide layer.

Claims

1. A method for forming a concave bottom oxide layer in a trench, comprising:

providing a semiconductor substrate;

forming a pad oxide layer on said semiconductor substrate;

forming a silicon nitride layer on said pad oxide layer;

etching said silicon nitride layer, said pad oxide layer and said semiconductor substrate to form said trench in said semiconductor substrate;

depositing a silicon oxide layer to refill into said trench and cover on said silicon nitride layer, wherein said silicon oxide layer has overhang portions at the silicon nitride corners of said trench;

anisotropically etching said silicon oxide layer to form a concave bottom oxide layer in said trench;

etching said silicon oxide layer to remove said silicon oxide layer on said silicon nitride layer and on sidewalls of said trench; and

removing said silicon nitride layer and said pad oxide layer.

2. The method according to claim 1, wherein said silicon oxide layer is deposited by using a plasma enhanced chemical vapor deposition (PECVD) process.

3. The method according to claim 1, wherein said silicon oxide layer is anisotropically etched by using a dry etching process.

4. The method according to claim 1, wherein said silicon oxide layer is anisotropically etched by using said overhang portions at said corners of said trench as an etching mask to protect said silicon oxide layer near said sidewalls at a bottom of said trench.

5. The method according to claim 1, wherein said concave bottom oxide layer serves as an insulating layer of a trench MOS to prevent said trench MOS from current leakage.

6. The method according to claim 1, wherein said silicon oxide layer is etched to remove said silicon oxide layer on said sidewalls of said trench and on said silicon nitride layer by using a wet etching process.

7. A method for forming a concave bottom oxide layer in a trench, comprising:

providing a semiconductor substrate;

forming a pad oxide layer on said semiconductor substrate;

forming a silicon nitride layer on said pad oxide layer;

etching said silicon nitride layer, said pad oxide layer and said semiconductor substrate to form said trench in said semiconductor substrate;

depositing a silicon oxide layer by using a plasma enhanced chemical vapor deposition (PECVD) process to refill into said trench and cover on said silicon nitride layer whereby overhang portions of said silicon oxide layer are formed at the silicon nitride corners of said trench;

anisotropically etching said silicon oxide layer to form a concave bottom oxide layer in said trench by using said overhang portions of said silicon oxide layer to protect said silicon oxide layer near sidewalls at a bottom of said trench;

etching said silicon oxide layer to remove said silicon oxide layer on said silicon nitride layer and on said sidewalls of said trench; and

removing said silicon nitride layer and said pad oxide layer.

8. The method according to claim 7, wherein said silicon oxide layer is anisotropically etched by using a dry etching process.

9. The method according to claim 7, wherein said concave bottom oxide layer serves as an insulating layer of a trench MOS to prevent said trench MOS from current leakage.

10. The method according to claim 7, wherein said silicon oxide layer is etched to remove said silicon oxide layer on said sidewalls of said trench and on said silicon nitride layer by using a wet etching process.

11. A method for forming a power MOS in a trench, comprising:

providing a semiconductor substrate;

forming a pad oxide layer on said semiconductor substrate;

forming a silicon nitride layer on said pad oxide layer;

etching said silicon nitride layer, said pad oxide layer and said semiconductor substrate to form said trench in said semiconductor substrate;

depositing a silicon oxide layer by using a plasma enhanced chemical vapor deposition (PECVD) process to refill into said trench and cover on said silicon nitride layer whereby overhang portions of said silicon oxide layer are formed at the silicon nitride corners of said trench;

anisotropically etching said silicon oxide layer to form a concave bottom oxide layer in said trench by using said overhang portions of said silicon oxide layer to protect said silicon oxide layer near sidewalls at a bottom of said trench;

etching said silicon oxide layer to remove said silicon oxide layer on said silicon nitride layer and on said sidewalls of said trench;

removing said silicon nitride layer and said pad oxide layer; and

forming said power MOS in said trench.

12. The method according to claim 11, wherein said silicon oxide layer is anisotropically etched by using a dry etching process.

13. The method according to claim 11, wherein said concave bottom oxide layer serves as an insulating layer of said power MOS to prevent said power MOS from discharging.

14. The method according to claim 11, wherein said silicon oxide layer is etched to remove said silicon oxide layer on said sidewalls of said trench and on said silicon nitride layer by using a wet etching process.