Method and system for reducing ARC layer removal by condensing the ARC layer

• US 6,265,751 B1
• Filed: 10/29/1999
• Issued: 07/24/2001
• Est. Priority Date: 10/29/1999
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Ogle, Robert B., Plat, Marina V.
• Primary Examiner(s): Loke, Steven
• Assistant Examiner(s): Owens, Douglas W.
• Application Number:
  US09/430,335
• Time in Patent Office: 634 Days
• Field of Search: 257/296, 257/437, 438/69, 438/72
• US Class Current: 257/437
• CPC Class Codes: H01L 21/0276 using an anti-reflective coating anti-reflective coating for lithography in general G03F7/09
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/42 Simultaneous manufacture of periphery and memory cells
• CPC Class Codes: H10B 99/00 Subject matter not provided for in other groups of this subclass

Abstract

A method and system for providing a semiconductor device is disclosed. The method and system include depositing an antireflective coating (ARC) layer. The ARC layer has a first thickness, as deposited, that is greater than a second, desired thickness of the ARC layer. The method and system further include condensing the ARC layer to the desired thickness. Consequently, the removal of the ARC layer during a photoresist strip is impeded.

Claims

1. A semiconductor device comprising:

a plurality of memory cells having a condensed antireflective coating (ARC) layer;

wherein the plurality of memory cells are defined using the ARC layer that is condensed from a first thickness to a second thickness prior to use in defining the plurality of memory cells, the second thickness being configured to reduce optical reflections during fabrication of the plurality of memory cells; and

wherein the condensed ARC layer is resistant to removal during a photoresist strip.

2. The semiconductor device of claim 1 wherein the ARC layer is condensed using a heat treatment at an elevated temperature.

3. The semiconductor device of claim 2 wherein the ARC layer includes a SiON layer which is condensed by the heat treating at a temperature of between 800 and 900 degrees Fahrenheit.

4. The semiconductor device of claim 1 wherein first thickness of the ARC layer is approximately thirty percent greater than the second thickness of the ARC layer.

5. The semiconductor device of claim 4 wherein the second thickness of the ARC layer is between two hundred and three hundred Angstroms and the first thickness of the ARC layer is approximately four hundred Angstroms.

6. The semiconductor device of claim 1 further comprising:

a plurality of logic cells;

wherein the plurality of logic cells are defined using the ARC layer that is condensed from a first thickness to a second thickness prior to use in defining the plurality of logic cells.

7. A semiconductor device, comprising:

a plurality of memory cells having a condensed antireflective coating (ARC) layer beneath a photoresist layer;

wherein the plurality of memory cells are defined using the ARC layer that is condensed from a first thickness to a second thickness prior to deposition of the photoresist layer, the second thickness being configured to reduce optical reflections during fabrication of the plurality of memory cells; and

wherein the condensed ARC layer is resistant to removal during a photoresist strip.