Current mode logic gates for low-voltage high speed applications

• US 6,265,898 B1
• Filed: 09/25/2000
• Issued: 07/24/2001
• Est. Priority Date: 07/13/1998
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Bellaouar, Abdellatif
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): Tran, Anh Q.
• Application Number:
  US09/669,025
• Time in Patent Office: 302 Days
• Field of Search: 326/29, 326/93, 326/99, 377/47, 377/48, 327/115, 327/117
• US Class Current: 326/93
• CPC Class Codes: H03K 19/086 Emitter coupled logic
• CPC Class Codes: H03K 19/09432 with coupled sources or source coupled logic H03K19/096 takes precedence

Abstract

A new family of current mode logic (CML) gates (14) which, in one embodiment includes OR/NOR and AND/NAND gates, as well as more complex logic functions. The circuit uses a complementary signal to drive the gate of a feedback transistor (19) which has the effect of pseudo differential operation. Although it uses only single-ended inputs (A, B), because of this feedback aspect, the circuit has many of the advantages of a differential circuit such as low-voltage operation, higher immunity to noise, and less sensitivity to parasitic elements.

Claims

1. A prescaler circuit, comprising:

an input buffer coupling input signals to clock and inverted clock signal inputs of first, second and third flip-flops;

a first input of said first flip-flop coupled to a first output of said second flip-flop;

a second input of said first flip-flop coupled to a first output of said third flip-flop;

a first output of said first flip-flop coupled to a first input of said second flip-flop and to a first clock input of a fourth flip-flop;

a second output of said first flip-flop coupled to a second input of said second flip-flop and to a second clock input of said fourth flip-flop;

a second output of said second flip-flop coupled to a first input of said third flip-flop;

a first output of said fourth flip-flop coupled to a second input of said third flip-flop and to a first clock input of a fifth flip-flop;

a second output of said fourth flip-flop coupled to a second clock input of said fifth flip-flop;

a third input of said third flip-flop coupled to the output of a logic gate;

a first input of said logic gate coupled to receive a select signal;

a first output of said fifth flip-flop coupled to a first clock input of a sixth flip-flop and to a second input of said logic gate;

a second output of said fifth flip-flop coupled to a second clock input of said sixth flip-flop;

a third input of said logic gate coupled to a first output of said sixth flip-flop.

2. The prescaler circuit of claim 1, further comprising an input buffer coupling said first and second inputs to said first and second clock inputs of said first, second and third flip-flops.

3. The prescaler circuit of claim 1, wherein said first clock input is a non-inverted clock input and said second clock input is an inverted clock input.

4. The prescaler circuit of claim 1, wherein:

said first output of said first flip-flop is a non inverted output and said second out put is an inverted output;

said first output of said second flip-flop is an inverted output and said second output is a non-inverted output; and

said first output of said third flip-flop is an inverted output and said second output is a non-inverted output,

said first output of said fourth flip-flop is an inverted output and said second output is a non-inverted output,

said first output of said fifth flip-flop is an inverted output and said second output is a non-inverted output,

said first output of said sixth flip-flop is an inverted output and said second output is a non-inverted output.