Integrated RF power sensor that compensates for bias changes

• US 6,265,943 B1
• Filed: 01/27/2000
• Issued: 07/24/2001
• Est. Priority Date: 01/27/2000
• Status: Expired due to Term

• Current Assignee: Qorvo US, Inc. (Qorvo, Inc.)
• Original Assignee: RF Micro Devices Incorporated (Qorvo, Inc.)
• Inventors: Dening, David C., Augustine, Paul J.
• Primary Examiner(s): Pascal, Robert
• Assistant Examiner(s): Choe, Henry
• Application Number:
  US09/492,211
• Time in Patent Office: 544 Days
• Field of Search: 330/285, 330/296, 330/295
• US Class Current: 330/296
• CPC Class Codes: H03F 1/0261 with control of the polarisation voltage or current, e.g. gliding Class A
• CPC Class Codes: H03F 2200/504 the supply voltage or current being continuously controlled by a controlling signal, e.g. the controlling signal of a transistor implemented as variable resistor in a supply path for, an IC-block showed amplifier

Abstract

A system for controlling a bias circuit by sensing RF amplifier output power and compensating for a dominating quiescent bias current includes an amplifier transistor and two sampling transistors. The two sampling transistors are physically smaller than the amplifier transistor, and are preferably the same size. The first sampling transistor is configured to sample the same RF input signal that is amplified by the amplifier transistor. The second sampling transistor is configured to receive and amplify only a bias network signal. The bias network associated with the transistors includes a selection of components based upon operating parameters as well as actual physical sizes of the transistors. The selection of component values in association with transistor sizes is used to enable generation of a current sensing signal that is proportional to the power level of the RF output signal generated by the amplifier transistor. The bias current to the amplifier transistor is controlled by an operational amplifier that is fed with a reference voltage and the dc bias detected by the second small transistor.

Claims

1. A system for sensing RF amplifier output power and controlling a bias circuit comprising:

a RF amplifier transistor configured to receive and amplify a RF signal;

a first sampling transistor configured to receive and amplify the RF signal wherein the first sampling transistor is physically smaller than the RF amplifier transistor such that the first sampling transistor is capable of producing a proportionally smaller amplified RF signal than that capable of being produced by the RF amplifier transistor for a RF input signal common to both the RF amplifier transistor and the first sampling transistor;

a second sampling transistor configured to receive and amplify a bias circuit signal;

a first current sensing circuit configured to receive a RF signal amplified by the first sampling transistor and generate a RF current proportional to a RF signal amplified by the RF amplifier transistor;

a second current sensing circuit configured to receive a bias circuit signal amplified by the second sampling transistor and generate a bias network current; and

a feedback configured to be responsive to the bias circuit current and generate the bias circuit signal.

2. The system according to claim 1 wherein the first and second sampling transistors are of equal size.

3. The system according to claim 1 wherein the second sampling transistor is configured to not receive the RF signal.

4. The system according to claim 1 wherein the bias circuit signal generated by the feedback establishes a quiescent operating point for the RF amplifier transistor, the first sampling transistor, and the second sampling transistor.

5. The system according to claim 1 wherein the feedback is an operational amplifier.

6. The system according to claim 1 further comprising a first bias resistor associated with the RF amplifier transistor.

7. The system according to claim 6 further comprising a second bias resistor associated with the first sampling transistor and a third bias resistor associated with the second sampling transistor.

8. The system according to claim 7 wherein a ratio of resistor values between the first bias resistor and the second bias resistor are substantially equal to a ratio of physical sizes between the first sampling transistor and the RF amplifier transistor.

9. The system according to claim 7 wherein a ratio of resistor values between the first bias resistor and the third bias resistor are substantially equal to a ratio of physical sizes between the second sampling transistor and the RF amplifier transistor.

10. The system according to claim 1 further comprising a first RF signal coupling capacitor configured to pass the RF signal to the RF amplifier transistor.

11. The system according to claim 10 further comprising a second RF signal coupling capacitor configured to pass the RF signal to the first sampling transistor.

12. The system according to claim 11 wherein a ratio of capacitor values between the first RF signal coupling capacitor and the second RF signal coupling capacitor are substantially equal to a ratio of physical sizes between the RF amplifier transistor and the first sampling transistor.

13. A system for sensing RF amplifier output power and controlling a bias circuit comprising:

a RF amplifier having an amplifier transistor and further having a first RF signal input port and a first RF signal output port;

a first sampling amplifier having a first sampling transistor, a second RF signal input port coupled to the first RF signal input port, and a second RF signal output port wherein the first sampling transistor is physically smaller than the amplifier transistor;

a second sampling amplifier having a second amplifying transistor, a first bias circuit input port, and a first bias circuit output port;

a first current sensing network having a third RF signal input port and a first voltage input port, wherein the third RF signal input port is coupled to the second RF signal output port;

a second current sensing network having a second bias circuit input port and a second voltage input port, wherein the second bias circuit input port is coupled to the first bias circuit output port; and

a feedback configured to be responsive to the second current sensing network and generate a bias circuit signal.

14. The system according to claim 13 wherein the first and second sampling transistors are of equal size.

15. The system according to claim 13 wherein the second sampling transistor does not include an RF signal input port.

16. The system according to claim 13 wherein the bias circuit signal generated by the feedback establishes a quiescent operating point for the first RF amplifier transistor, the sampling transistor, and the second sampling transistor.

17. The system according to claim 13 wherein the feedback is an operational amplifier.

18. The system according to claim 13 further comprising a first bias resistor coupled at one end to the amplifier transistor and coupled at an opposite end to the feedback.

19. The system according to claim 18 further comprising a second bias resistor coupled at one end to the first sampling transistor and coupled at an opposite end to the feedback.

20. The system according to claim 19, wherein a ratio of resistor values between the first bias resistor and the second bias resistor is substantially equal to a ratio of physical sizes between the first sampling transistor and the amplifier transistor.

21. The system according to claim 19 further comprising a third bias resistor coupled at one end to the second sampling transistor and coupled at an opposite end to the feedback.

22. The system according to claim 21, wherein a ratio of resistor values between the first bias resistor and the third bias resistor is substantially equal to a ratio of physical sizes between the second sampling transistor and the amplifier transistor.

23. The system according to claim 13 further comprising a first RF signal coupling capacitor coupled at one end to the first and second RF signal input port and coupled at an opposite end to the amplifier transistor.

24. The system according to claim 23 further comprising a second RF signal coupling capacitor coupled at one end to the first and second RF signal input port and coupled at an opposite end to the first sampling transistor.

25. The system according to claim 24 wherein a ratio of capacitor values between the first RF signal coupling capacitor and the second RF signal coupling capacitor is substantially equal to a ratio of physical sizes between the amplifier transistor and the first sampling transistor.

26. A system for sensing RF amplifier output power and controlling a bias circuit comprising:

amplifying means for amplifying a RF input signal and generating a RF output signal therefrom;

first sampling means for sampling the RF input signal that is associated with the amplifying means and generating a sampled RF signal therefrom;

second sampling means for sampling a bias circuit signal and generating a sampled bias circuit signal therefrom;

first sensing means for sensing the sampled RF signal and generating a current sensing signal therefrom proportional to a power amplitude associated with the RF output signal;

second sensing means for sensing the sampled bias circuit signal and generating a bias sensing signal therefrom; and

feedback means for responding to the bias sensing signal and generating the bias circuit signal.

27. The system according to claim 26 wherein the bias circuit signal generated by the feedback means establishes a quiescent operating point for the amplifying means, the first samplings means, and the second samplings means.

28. The system according to claim 26 wherein the amplifying means comprises a first transistor.

29. The system according to claim 28 wherein the first sampling means comprises a second transistor, the second transistor being configured to be physically smaller than the first transistor such that a ratio of currents associated with the amplifying means and the first sampling means is equal to a ratio of physical sizes associated with the first and second transistors.

30. The system according to claim 29 wherein the second sampling means comprises a third transistor, the third transistor being configured to be physically smaller than the first transistor such that a ratio of currents associated with the amplifying means and the second sampling means is equal to a ratio of physical sizes associated with the first and third transistors.

31. The system according to claim 30 wherein the second and third transistors are of equal physical size.

32. A method for sensing RF signal power amplitude and controlling a bias circuit, the method comprising the steps of:

(a) providing a RF signal amplifier comprising a first transistor having a first predetermined size;

(b) providing a first sampling amplifier comprising a second transistor having a second predetermined size that is smaller than the first predetermined size;

(c) providing a second sampling amplifier comprising a third transistor having a third predetermined size that is smaller than the first predetermined size;

(d) amplifying a RF input signal to produce a first RF output signal;

(e) sampling the RF input signal to produce a second RF output signal proportional to the first RF output signal, wherein the proportion is associated with a ratio determined by the first and second predetermined sizes;

(f) sampling a bias circuit signal to produce a bias circuit output signal; and

(g) controlling a bias circuit by responding to the bias circuit output signal and generating the bias circuit signal.

33. A system for sensing RF amplifier output power comprising:

a RF amplifier transistor configured to receive and amplify a RF signal;

a first sampling transistor configured to receive and amplify the RF signal, wherein the first sampling transistor is physically smaller than the RF amplifier transistor such that the first sampling transistor is capable of producing a proportionally smaller amplified RF signal than that capable of being produced by the RF amplifier transistor for a RF input signal common to both the RF amplifier transistor and the first sampling transistor;

a second sampling transistor configured to receive and amplify a bias circuit signal, wherein the second sampling transistor is physically smaller than the RF amplifier transistor;

a first current sensing circuit configured to receive a RF signal amplified by the first sampling transistor and generate a current proportional to a power amplitude associated with the RF signal amplified by the RF amplifier transistor;

a second current sensing circuit configured to receive a bias circuit signal amplified by the second sampling transistor and generate a sampled bias circuit current;

a feedback configured to be responsive to the sampled bias circuit current and generate the bias circuit signal to establish a quiescent operating point for the RF amplifier transistor, the first sampling transistor, and the second sampling transistor;

a first bias resistor associated with the RF amplifier transistor; and

a second bias resistor associated with the first sampling transistor; and

a third bias resistor associated with the second sampling transistor;

wherein a ratio of resistor values between the first bias resistor and the second bias resistor is substantially equal to a ratio of physical sizes between the first sampling transistor and the RF amplifier transistor and wherein a ratio of resistor values between the first bias resistor and the third bias resistor is substantially equal to a ratio of physical sizes between the second sampling transistor and the RF amplifier transistor.