Stepper and scanner new exposure sequence with intra-field correction

• US 6,266,144 B1
• Filed: 08/26/1999
• Issued: 07/24/2001
• Est. Priority Date: 08/26/1999
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Li, Meng Chun
• Primary Examiner(s): Font, Frank G.
• Assistant Examiner(s): Punnoose, Roy M.
• Application Number:
  US09/383,598
• Time in Patent Office: 698 Days
• Field of Search: 356/363, 356/237.1, 356/237.2, 356/237.4, 356/237.5, 356/401
• US Class Current: 356/401
• CPC Class Codes: G03F 7/70425 Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
• CPC Class Codes: G03F 7/70433 Layout for increasing efficiency or for compensating imaging errors, e.g. layout of exposure fields for reducing focus errors; Use of mask features for increasing efficiency or for compensating imaging errors
• CPC Class Codes: G03F 7/70633 Overlay, i.e. relative alignment between patterns printed by separate exposures in different layers, or in the same layer in multiple exposures or stitching

Abstract

A method and system are provided for determining the degree of overlay misregistration when exposing a semiconductor wafer having a center and a periphery comprises the following steps. Expose the wafer with a scan in a sequence from the center of the wafer to the periphery. Select dies on the periphery of a wafer for measurement which represent a maximum degree of distortion, and employ a correction algorithm for calculating an intrafield reduction ratio to minimize heat expansion.

Claims

1. A method of determining the degree of overlay misregistration when using a reticle to expose a semiconductor wafer having a center and a periphery comprises the steps as follows:

(a) calculate a field exposure sequence by radius,

(b) provide fields of the same radius with a correction factor,

(c) cause exposure through the reticle,

(d) perform overlay measurement to gain raw data and a revised correction factor, and

(e) feed back the revised correction factor to step (b).

5. A method in accordance with claim 1 including scanning in a radial direction.

6. A method in accordance with claim 1 including scanning outwardly along a spiraling path.

8. A system in accordance with claim 5 including means for selection of dies on the periphery of a wafer for measurement which represent a maximum degree of distortion.

2. A method of determining the degree of overlay misregistration when exposing a semiconductor wafer having a center and a periphery comprising:

exposing the wafer with a scan in a sequence from the center of the wafer to the periphery including selection of dies on the periphery of a wafer for measurement which represent a maximum degree of distortion, and

employing a correction algorithm for calculating an intrafield reduction ratio to minimize heat expansion.

3. A method in accordance with claim 2 including scanning in a radial direction.

4. A method in accordance with claim 2 including scanning outwardly along a spiraling path.

7. A system for determining the degree of overlay misregistration when exposing a semiconductor wafer having a center and a periphery comprises means for exposing the wafer with a scan in a sequence from the center of the wafer to the periphery including:

(a) calculation means for calculating a field exposure sequence by radius,

(b) correction means for providing fields of the same radius with a correction factor,

(c) exposure means for causing exposure through the reticle,

(d) measurement means for performing overlay measurement to gain raw data and a revised correction factor, and

(e) feedback means for feeding back the revised correction factor to the correction means.

9. A system in accordance with claim 7 including means for employing a correction algorithm for calculating an intrafield reduction ratio to minimize heat expansion.

10. A system in accordance with claim 9 including means for scanning in a radial direction.

11. A system in accordance with claim 9 including means for scanning outwardly along a spiraling path.

12. A system in accordance with claim 7 including:

means for selection of dies on the periphery of a wafer for measurement which represent a maximum degree of distortion, and

means for employing a correction algorithm for calculating an intrafield reduction ratio to minimize heat expansion.

13. The system of claim 7 including:

means for selecting dies on the periphery of a wafer for measurement which represent a maximum degree of distortion, and

means for employing a correction algorithm for calculating an intrafield reduction ratio to minimize heat expansion.

14. A system in accordance with claim 13 including means for scanning in a radial direction.

15. A system in accordance with claim 13 including means for scanning outwardly along a spiraling path.