Word line straps using two different layers of metal

• US 6,266,264 B1
• Filed: 02/07/2000
• Issued: 07/24/2001
• Est. Priority Date: 02/13/1999
• Status: Expired due to Term

• Current Assignee: InnoMemory, LLC (Jeffrey M. Gross)
• Original Assignee: Integrated Device Technology Incorporated (Renesas Electronics Corporation)
• Inventors: Proebsting, Robert J.
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): LE, THONG QUOC
• Application Number:
  US09/499,265
• Time in Patent Office: 533 Days
• Field of Search: 365/63, 365/51, 365/52, 365/230.06
• US Class Current: 365/63
• CPC Class Codes: G11C 11/408 Address circuits
• CPC Class Codes: G11C 2207/229 Timing of a write operation
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
• CPC Class Codes: H10B 12/488 Word lines
• CPC Class Codes: H10B 12/50 Peripheral circuit region structures

Abstract

A memory cell in a memory device. The memory cell has a word line structure that includes a polysilicon layer, a first metal layer, and a second metal layer. The polysilicon layer is configured with word lines. Half of the polysilicon word lines are strapped to corresponding word lines configured in the first metal layer and the remaining polysilicon word lines are strapped to corresponding word lines configured in the second metal layer.

Claims

1. A word line structure in a memory device, the word line structure comprising:

a polysilicon layer;

a first metal layer; and

a second metal layer;

wherein the polysilicon layer is configured with word lines; and

wherein substantially half of the polysilicon word lines are strapped to corresponding word lines configured in the first metal layer and remaining polysilicon word lines are strapped to corresponding word lines configured in the second metal layer.

2. A word line structure in accordance with claim 1 wherein the first metal layer and the second metal layer are the two lowest metal layers in the memory device with respect to any other metal layers in the memory device.

3. A word line structure in accordance with claim 1 wherein adjacent polysilicon word lines are grouped into pairs, and wherein pairs are alternatingly strapped to the first metal layer and the second metal layer.

4. A memory device including at least one memory cell array, the memory cell array including a word line structure comprising:

a polysilicon layer;

a first metal layer; and

a second metal layer;

wherein the polysilicon layer is configured with word lines; and

wherein substantially half of the polysilicon word lines are strapped to corresponding word lines configured in the first metal layer and remaining polysilicon word lines are strapped to corresponding word lines configured in the second metal layer.

5. A memory device in accordance with claim 4 wherein the first metal layer and the second layer are the two lowest metal layers in the memory device with respect to any other metal layers in the memory device.

6. A memory device in accordance with claim 4 wherein adjacent polysilicon word lines are grouped into pairs, and wherein pairs are alternatingly strapped to the first metal layer and the second metal layer.

7. A memory device in accordance with claim 4 wherein the memory device comprises a plurality of memory cells.

8. A memory device in accordance with claim 4 wherein the memory device is configured as a DRAM.

9. A memory device in accordance with claim 8 wherein the first metal layer and the second metal layer are the two lowest metal layers in the memory device with respect to any other metal layers in the memory device.

10. A memory device in accordance with claim 8 wherein adjacent polysilicon word lines are grouped into pairs, and wherein pairs are alternatingly strapped to the first metal layer and the second metal layer.

11. A memory device in accordance with claim 8 wherein the memory device comprises a plurality of memory cells.

12. A method of creating word lines within a memory device, the method comprising:

providing a polysilicon layer;

defining the polysilicon layer into word lines;

depositing a first insulating layer over the polysilicon layer;

defining first and second vias in the insulating layer;

depositing a first layer of metal on the insulating layer;

defining first metal word lines and via islands in the first metal layer;

depositing a second insulating layer on the first layer of metal;

configuring the second insulating layer with third vias;

depositing a second layer of metal over the second insulating layer; and

defining second metal word lines in the second metal layer;

wherein the layers are configured such that each first via is in communication with a word line in the first metal layer and a word line in the polysilicon layer, and each second and each third via are in communication with a word line in the second metal layer and a word line in the polysilicon layer.

13. A method in accordance with claim 12 wherein the vias are etched.

14. A method in accordance with claim 13 further comprising providing each via with a conductive plug.

15. A method in accordance with claim 12 wherein the word lines are defined by etching.