Method for forming gate segments for an integrated circuit

• US 6,266,268 B1
• Filed: 10/29/1999
• Issued: 07/24/2001
• Est. Priority Date: 04/25/1997
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Noble, Wendell P.
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): LE, THONG QUOC
• Application Number:
  US09/430,442
• Time in Patent Office: 634 Days
• Field of Search: 365/230.08, 365/149, 365/188, 365/208, 365/196, 365/230.06, 365/182, 365/161, 438/624, 438/692
• US Class Current: 365/149
• CPC Class Codes: H10B 12/033 the capacitor extending over the transistor
• CPC Class Codes: H10B 12/05 Making the transistor

Abstract

A method for forming gate segments in an integrated circuit. The method begins by forming a shallow trench isolation region outwardly from a layer of semiconductor material to isolate a plurality of active regions of the integrated circuit. After the isolation region is formed, at least one gate segment is formed in each active region by depositing, planarizing and selectively etching a conductive material. Source/drain regions are also formed in the active region. The active regions are selectively interconnected with edge-defined conductors that pass outwardly from the gate segments and the shallow trench isolation region to form the integrated circuit.

Claims

1. A memory device, comprising:

an array of memory cells interconnected with a plurality of bit lines and word lines, wherein each cell includes an activation device with gates formed as segments that are separated by, and are self-aligned with, a shallow trench isolation region;

an addressing circuit that is coupled to the array of memory cells to allow selective access to the memory cells; and

wherein the word lines comprise sub-lithographic word lines and the gate segments for the activation device are formed after the shallow trench isolation region and before the source and drain are doped.

2. The memory device of claim 1, wherein the array of memory cells comprises a plurality of cells that are formed in a folded bit line configuration.

3. The memory device of claim 1, wherein the cells of the memory device include stacked capacitors for storing data.

4. An integrated circuit, comprising:

a shallow trench isolation region with a pad that extends outwardly from a layer of semiconductor material to isolate a plurality of active regions of the integrated circuit, wherein the pad is removed outwardly from the active regions;

a thin insulating layer formed outwardly from the active regions;

a conductive layer formed outwardly from the insulating layer, wherein the conductive layer is planarized such that a working surface of the conductive layer is substantially coplanar with a surface of the shallow trench isolation region;

at least one gate segment in each active region, wherein the at least one gate segment is formed by selectively removing portions of the conductive layer and the insulating layer from the active regions;

a plurality of source/drain regions formed in the portions of the active regions not covered by the conductive layer; and

wherein the active regions are selectively interconnected with conductors that pass outwardly from the gate segments and the shallow trench isolation region to form the integrated circuit.

5. The integrated circuit of claim 4, further comprising:

a number of edge-defined word lines that selectively interconnect the gate segments to form an array of memory cells;

a bit line coupled to a source/drain region of each memory cell; and

at least one storage capacitor coupled to a source/drain region for each memory cell.

6. The integrated circuit of claim 4, wherein at least one gate segment comprises two gate segments in each active region.

7. The integrated circuit of claim 4, wherein conductors comprises edge-defined conductors.

8. The integrated circuit of claim 4, wherein the at least one storage capacitor comprises at least two storage capacitors.

9. A memory device, comprising:

a shallow trench isolation region that extends outwardly from active regions of a semiconductor material to form active regions;

a thin insulating layer disposed outwardly from the active regions;

a conductive layer disposed outwardly from the insulating layer, wherein the conductive layer is planarized such that a working surface of the conductive layer is substantially coplanar with a surface of the shallow trench isolation region;

at least one gate segment in each active region, wherein the at least one gate segment is formed by selectively removing portions of the conductive layer and the insulating layer from the active regions;

a plurality of source/drain regions formed in the portions of the active regions not covered by the conductive layer;

a plurality of word lines which are selectively interconnected with the gate segments; and

a plurality of bit lines and storage capacitors that are selectively coupled to the source/drain regions to form an array of cells for the memory device.

10. The memory device of claim 9, wherein the conductive layer comprises a deposited poly-silicon layer.

11. The memory device of claim 9, wherein the gate segments which are interconnected with word lines comprise gate segments which form a folded bit line array of memory cells.

12. The memory device of claim 9, wherein the shallow trench isolation region comprises a trench etched into the layer of semiconductor material that is filled with an oxide layer, wherein the trench isolates a number of active regions and an oxide layer that fills the trench.

13. The memory device of claim 9, wherein the gate segments which are interconnected with word lines comprise gate segments which are interconnected with edge-defined word lines.

14. The memory device of claim 9, wherein at least one gate segment comprises two gate segments in each active region.

15. A memory system, comprising:

a processor;

a memory device coupled to the processor, wherein the memory device comprises;

an array of memory cells interconnected with a plurality of bit lines and word lines, wherein each cell includes an activation device with gates formed as segments that are separated by and self-aligned with a shallow trench isolation region;

an addressing circuit that is coupled to the array of memory cells to allow selective access to the memory cells; and

wherein the word lines comprise sub-lithographic word lines and a conductive material and insulating material for the gate segments for the activation devices are deposited after the shallow trench isolation region is formed and before the source and drain are doped.

16. The memory system of claim 15, wherein the array of memory cells comprises a plurality of cells that are formed in a folded bit line configuration.

17. The memory system of claim 15, wherein the cells of the memory device include stacked capacitors for storing data.

18. The memory system of claim 15, wherein the memory device is a dynamic random access memory.

19. A memory system, comprising:

a control circuit;

a memory device coupled to the processor, wherein the memory device comprises;

a shallow trench isolation region with a pad that extends outwardly from active regions of a semiconductor material to form active regions;

a thin insulating layer disposed outwardly from the active regions;

a conductive layer disposed outwardly from the insulating layer, wherein the conductive layer is planarized such that a working surface of the conductive layer is substantially coplanar with a surface of the shallow trench isolation region;

at least one gate segment in each active region, wherein the at least one gate segment is formed by selectively removing portions of the conductive layer and the insulating layer from the active regions;

a plurality of source/drain regions formed in the portions of the active regions not covered by the conductive layer;

a plurality of word lines which are selectively interconnected with the gate segments; and

a plurality of bit lines and storage capacitors that are selectively coupled to the source/drain regions to form an array of cells for the memory device.

20. The memory system of claim 19, wherein the control circuit comprises a microprocessor.

21. The memory system of claim 19, wherein the memory device is a dynamic random access memory.

22. The memory system of claim 19, wherein the conductive layer comprises a deposited poly-silicon layer.

23. The memory system of claim 19, wherein the gate segments which are interconnected with word lines comprise gate segments which form a folded bit line array of memory cells.

24. The memory system of claim 19, wherein the shallow trench isolation region comprises a trench etched into the layer of semiconductor material that is filled with an oxide layer, wherein the trench isolates a number of active regions.

25. The memory system of claim 19, wherein the gate segments which are interconnected with word lines comprise gate segments which are interconnected with edge-defined word lines.

26. The memory system of claim 19, wherein at least one gate segment comprises two gate segments in each active region.

27. A pair of memory cells for an integrated circuit formed using a lithographic process having a minimum lithographic dimension, comprising:

two transistors formed in semiconductor material, the transistors having a shared drain, each transistor having a gate and a source, the gate of each transistor formed as segments that are separated by and self-aligned with a shallow trench isolation region, wherein the gate of each transistor extends outwardly from the semiconductor material;

two word lines formed outwardly from the transistors, wherein the word lines comprise sub-lithographic word lines and each word line having a width less than the minimum lithographic dimension, each word line connected to a gate of a different transistor, the word lines for activating the transistors;

a bit line and two conductors formed outwardly from the transistors, the bit line connected to the shared drain of the transistors, each conductor connected to the source of a different transistor, the bit line and the two conductors adjacent to the word lines; and

two storage capacitors formed outwardly from the bit line and the conductors, each storage capacitor coupled to a source of a different transistor by one of the conductors.

28. An electronic system comprising:

a microprocessor;

a memory device coupled to the microprocessor, wherein the memory device comprises;

a column decoder with input output circuitry coupled to a plurality of bit lines and a plurality of bit complement lines;

a row decoder coupled to a plurality of word lines;

at least one address buffer coupled to the row decoder and column decoder, wherein the address buffer receives an address of a selected cell and identifies a word line of the selected cell to the row decoder;

a plurality of sense amplifiers, wherein each sense amplifier is coupled to a corresponding pair of bit line and bit complement line;

an array of memory cells interconnected with the plurality of bit lines and word lines, wherein each cell includes an activation device with gates formed as segments that are separated by and self-aligned with a shallow trench isolation region; and

wherein the word lines comprise sub-lithographic word lines and conductive material of the gate segments for the activation devices are formed after the shallow trench isolation region is formed and before the source and drain are doped.

29. The electronic system of claim 28, wherein the array of memory cells comprises a plurality of cells that are formed in a folded bit line configuration.

30. The electronic system of claim 28, wherein the cells of the memory device include stacked capacitors for storing data.