Method of operating a memory device having write latency

• US 6,266,285 B1
• Filed: 05/08/2000
• Issued: 07/24/2001
• Est. Priority Date: 04/18/1990
• Status: Expired due to Fees

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Horowitz, Mark, Farmwald, Michael
• Primary Examiner(s): NGUYEN, TAN
• Application Number:
  US09/566,551
• Time in Patent Office: 442 Days
• Field of Search: 365/233, 365/194, 365/233.5, 365/189.05
• US Class Current: 365/194
• CPC Class Codes: G06F 11/006 Identification G06F11/2289 takes precedence
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 12/0215 with look ahead addressing means
• CPC Class Codes: G06F 12/0661 and decentralised selection
• CPC Class Codes: G06F 12/0684 with feedback, e.g. presence or absence of unit detected by addressing, overflow detection
• CPC Class Codes: G06F 13/1605 based on arbitration arbitration in handling access to a common bus or bus system G06F13/36
• CPC Class Codes: G06F 13/161 with latency improvement
• CPC Class Codes: G06F 13/1678 using bus width
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 13/376 using a contention resolving method, e.g. collision detection, collision avoidance
• CPC Class Codes: G06F 13/4239 with asynchronous protocol
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 2207/105 Aspects related to pads, pins or terminals
• CPC Class Codes: G11C 2207/108 Wide data ports
• CPC Class Codes: G11C 29/88 with partially good memories
• CPC Class Codes: G11C 5/00 Details of stores covered by group G11C11/00
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: G11C 5/063 : Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 5/066 : Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
• CPC Class Codes: G11C 7/1006 : Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1012 : Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
• CPC Class Codes: G11C 7/1045 : Read-write mode select circuits
• CPC Class Codes: G11C 7/1051 : Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1057 : Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/1066 : Output synchronization
• CPC Class Codes: G11C 7/1069 : I/O lines read out arrangements
• CPC Class Codes: G11C 7/1072 : for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/1078 : Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1084 : Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/22 : Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 : Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: G11C 7/225 : Clock input buffers
• CPC Class Codes: G11C 8/00 : Arrangements for selecting an address in a digital store for stores using transistors G11C11/407, G11C11/413
• CPC Class Codes: Y02D 10/00 : Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A method of operation of a memory device. The memory device including a section of memory having a plurality of memory cells. The method of operation comprises receiving a request for a write operation and sampling a first portion of data after a delay time transpires in response to the request for a write operation. A method of controlling the memory device comprises issuing a request for a write operation to the memory device. The memory device samples data after a number of clock cycles of the external clock signal transpire in response to the request. The method of controlling also comprises issuing a first portion of data to the memory device after the number of clock cycles of the external clock signal transpire.

Claims

1. A method of operation in a memory device having a section of memory which includes a plurality of memory cells, the method comprising:

receiving a request for a write operation synchronously with respect to an external clock signal; and

sampling data, in response to the request for a write operation, after a programmable delay time transpires.

2. The method of claim 1 further including receiving an external clock signal, wherein the data is sampled synchronously with respect to the external clock signal.

3. The method of claim 2 wherein the data includes a first portion of data and a second portion of data, and wherein the first portion of data is sampled in response to a rising edge transition of the external clock signal and the second portion of data is sampled in response to a falling edge transition of the external clock signal.

4. The method of claim 2 wherein the external clock signal is a clock signal having a fixed frequency.

5. The method of claim 1 wherein the programmable delay time is representative of a number of clock cycles of an external clock signal to transpire before the data is sampled in response to the request for a write operation.

6. The method of claim 1 further including storing a value which is representative of the programmable delay time in a programmable register on the memory device.

7. The method of claim 6 further including storing the value in the programmable register in response to a set register request.

8. The method of claim 1 wherein the programmable delay time is a fixed amount of time.

9. The method of claim 1 wherein the request for a write operation includes an operation code and the method further includes receiving block size information which defines an amount of data to be sampled in response to a request for a write operation.

10. The method of claim 1 wherein receiving the request for a write operation includes sampling an operation code synchronously with respect to a first transition of the external clock signal.

11. The method of claim 10 wherein receiving the request for a write operation further includes sampling address information, synchronously with respect to a second transition of the external clock signal.

12. The method of claim 11 wherein the first transition of the external clock signal is a rising edge of the external clock signal and the second transition of the external clock signal is a falling edge of the external clock signal.

13. A method of operation in a memory device having a section of memory which includes a plurality of memory cells, the method comprising:

receiving an external clock signal;

receiving a request for a write operation synchronously with respect to the external clock signal; and

sampling data, in response to the request for a write operation, after a programmable number of clock cycles of the external clock signal transpire.

14. The method of claim 13 wherein the data includes a first portion of data and a second portion of data, and wherein the first portion of data is sampled in response to a rising edge transition of the external clock signal and the second portion of data is sampled in response to a falling edge transition of the external clock signal.

15. The method of claim 13 further including storing a value which is representative of the programmable number of clock cycles of the external clock in a programmable register on the memory device.

16. The method of claim 15 further including receiving a set register request, wherein in response to the set register request, the memory device stores the value in the register.

17. The method of claim 15 further including receiving the value during an initialization sequence and after power is applied to the device.

18. The method of claim 13 wherein the request for a write operation includes an operation code and the method further includes receiving block size information which defines an amount of data to be sampled in response to a request for a write operation.

19. A method of controlling a memory device by a controller, the memory device having a section of memory which includes a plurality of memory cells, the method comprising:

issuing a request for a write operation to the memory device synchronously with respect to an external clock;

issuing data to the memory device after a predetermined delay time transpires; and

wherein, in response to the request for a write operation, the memory device samples the data after the predetermined delay time transpires.

20. The method of claim 19 wherein the delay time is representative of a number of clock cycles of an external clock signal to transpire before the memory device samples data in response to the request.

21. The method of claim 19 wherein the first portion of data is issued synchronously with respect to an external clock signal.

22. The method of claim 21 wherein the data includes a first portion of data and a second portion of data, and wherein the first portion is issued synchronously with respect to a rising edge transition of the external clock signal and the second portion is issued synchronously with respect to a falling edge transition of the external clock signal.

23. The method of claim 21 wherein the external clock signal is a clock signal having a fixed frequency.

24. The method of claim 19 further including:

providing the value to the memory device; and

issuing a set register request to the memory device,

wherein the memory device stores the value which is representative of the predetermined delay time in a programmable register on the memory device.

25. The method of claim 24 further including issuing a set register request during an initialization sequence, wherein in response to the set register request, the memory device stores the value in the programmable register.

26. The method of claim 19 further including issuing block size information wherein the block size information defines an amount of data to be sampled by the memory device in response to the request for a write operation after the predetermined delay time transpires.

27. A method of controlling a synchronous memory device by a controller device, the memory device having a section of memory which includes a plurality of memory cells, wherein the synchronous memory device receives an external clock signal, the method comprising:

issuing a request for a write operation to the memory device;

issuing data to the memory device after a programmable number of clock cycles of the external clock signal transpire; and

wherein, in response to the request for a write operation, the memory device samples data after the programmable number of clock cycles of the external clock signal transpire.

28. The method of claim 27 wherein the data includes a first portion of data and a second portion of data, and wherein the first portion of data is issued synchronously with respect to the external clock signal.

29. The method of claim 28 wherein the first portion is issued synchronously with respect to a rising edge transition of the external clock signal and the second portion is issued synchronously with respect to a falling edge transition of the external clock signal.

30. The method of claim 29 wherein the external clock signal has a fixed frequency.

31. The method of claim 27 further including:

providing the value which is representative of the programmable number of clock cycles of the external clock signal to the memory device,

issuing a set register request, and

wherein the memory device stores the value in a programmable register on the memory device.

32. The method of claim 30 wherein the value and the set register request are issued in a first packet.

33. The method of claim 27 wherein the request for a write operation includes an operation code, the method further including issuing block size information to the memory device, wherein the block size information defines an amount of data to be sampled by the memory device in response to the request for a write operation.