Elastic store for wireless communication systems

• US 6,266,385 B1
• Filed: 12/23/1997
• Issued: 07/24/2001
• Est. Priority Date: 12/23/1997
• Status: Expired due to Fees

• Current Assignee: Hanger Solutions, LLC (IP Investments Group LLC)
• Original Assignee: Wireless Facilities Incorporated (Kratos Defense & Security Solutions Incorporated)
• Inventors: Safavi, Saeid, Lakkis, Ismail, Bui, Hoang Xuan, Roy, Joseph J., Tayebi, Masood K., Hatim, Baya, OʼShea, Deirdre, OʼScolai, Cathal
• Primary Examiner(s): Ghebretinsae, Temesghen
• Application Number:
  US08/997,150
• Time in Patent Office: 1,309 Days
• Field of Search: 375/372, 375/371, 370/516, 365/189.12, 711/109
• US Class Current: 375/372
• CPC Class Codes: H04J 3/0605 Special codes used as synchronising signal
• CPC Class Codes: H04J 3/07 using pulse stuffing for systems with different or fluctuating information rates or bit rates
• CPC Class Codes: H04W 84/14 WLL [Wireless Local Loop]; RLL [Radio Local Loop]

Abstract

A system and method of buffering data of a wireless communication system. The system and method maintain synchronization, end-to-end signaling and coding overhead bits needed to encapsulate data frames sent over wireless media. Additionally, the system and method compensate for transmitting and receiving clock variations. In one embodiment, the system uses framing of data with preamble, stuffing and signaling bits transmitted synchronously at a high data rate in the Industrial, Scientific and Medical (ISM) bands.

Claims

1. A synchronous elastic store system, comprising:

a shift register having a plurality of data bits, the shift register receiving a stream of digital input data and a single master clock input signal, wherein the digital input data is independent from the single master clock input signal;

an arbiter that arbitrates between a read request and a write request to the shift register, the arbiter having the single master clock as an input signal and providing a control signal to the shift register; and

a digital dejitter circuit receiving at least one status signal from the elastic store and providing a read request signal to the elastic store.

2. The system defined in claim 1, wherein the master clock is an input signal to the dejitter circuit.

3. The system defined in claim 1, wherein the at least one status signal comprises a near underflow signal and a near overflow signal.

4. The system defined in claim 1, wherein the at least one status signal comprises high and low limit signals for the shift register.

5. A synchronous digital elastic store system, comprising:

a shift register receiving a stream of digital input data and a master clock input signal, said master clock signal being independent of the digital input data;

an arbiter that arbitrates between a read request and a write request, the arbiter providing a control signal to the shift register and generating at least one counter control signal;

an up/down counter receiving the counter control signal from the arbiter and generating selector control signals; and

a selector circuit receiving data from the shift register and receiving selector control signals from the up/down counter, said selector circuit selecting one of the shift register bits to be read from the elastic store.

6. The system defined in claim 5, additionally comprising a register that latches the selected output of the selector circuit.

7. The system defined in claim 5, additionally comprising a plurality of comparators that generate status signals in response to the output of the up/down counter and predetermined status levels.

8. The system defined in claim 7, additionally comprising a digital dejitter circuit receiving a status signal from at least one of the comparators and providing a read request signal to the elastic store.

9. A synchronous elastic store system, comprising:

a channelizer;

a synchronous elastic store having a read/write arbiter, the synchronous elastic store receivably connected to the channelizer;

a framer being receivably connected to the synchronous elastic store; and

a wireless transmitter circuit receivably connected to the framer.

10. A synchronous elastic store system, comprising:

a wireless receiver circuit;

a deframer being receivably connected to the wireless receiver circuit;

a synchronous elastic store having a read/write arbiter, the synchronous elastic store receivably connected to the deframer; and

a dechannelizer receivably connected to the synchronous elastic store.

11. A synchronous elastic store system, comprising:

a shift register having a plurality of data bits, the shift register receiving a stream of digital input data and a single master clock input signal, wherein the digital input data is independent from the single master clock input signal; and

an arbiter that arbitrates between a read request and a write request to the shift register, the arbiter having the single master clock as an input signal and providing a control signal to the shift register,

wherein the elastic store is utilized in a communication system and includes a transmit elastic store and a receive elastic store, wherein the length of the shift register of the transmit elastic store is different than the length of the shift register of the receive elastic store.