Serial data transfer device

• US 6,266,710 B1
• Filed: 08/04/1998
• Issued: 07/24/2001
• Est. Priority Date: 08/04/1997
• Status: Expired due to Term

• Current Assignee: Robert Bosch GmbH
• Original Assignee: Robert Bosch GmbH
• Inventors: Schwarz, Franz, Dittmer, Bernd
• Primary Examiner(s): Etienne, Ario
• Application Number:
  US09/128,871
• Time in Patent Office: 1,085 Days
• Field of Search: 710/1, 710/58, 710/61, 710/60, 710/71
• US Class Current: 710/1
• CPC Class Codes: B60R 16/0315 using multiplexing techniques multiplexing for transmission of signals G08C15/00; multiplexing for electrical communication in general H04J
• CPC Class Codes: G06F 13/4045 where the bus bridge performs an extender function

Abstract

A data transfer device for unidirectional serial data transfer from a transmitting device to a receiving device, in particular from a microcontroller to an output stage IC of a motor vehicle control unit. The data transfer device includes a P/S converter provided in the transmitting device for converting a parallel data stream made available in the transmitting device into a serial data stream with transfer frames of a predefined format and for transmitting the serial data stream to the receiving device over a data transfer channel. The data transfer device also includes an S/P converter provided in the receiving device for converting the transmitted serial data stream back into a parallel data stream, and a clock signal generating device for generating a clock signal and for sending the clock signal to the P/S converter and the S/P converter to perform the conversion operations continuously and in-phase. In addition, the data transfer device includes a synchronizing device for generating a synchronizing signal according to the conversion operation of the P/S converter and for supplying the same to the S/P converter for synchronizing the conversion operations.

Claims

1. A data transfer device for unidirectionally and serially transferring data from a transmitting device to a receiving device, comprising:

a parallel-to-serial (P/S) converter provided in the transmitting device, the P/S converter performing a first conversion operation by converting a parallel data stream in the transmitting device to a serial data stream, the P/S converter transmitting the serial data stream to the receiving device via a data transfer channel, the serial data stream including transfer frames which have a predefined format;

a serial-to-parallel (S/P) converter provided in the receiving device, the S/P converter performing a second conversion operation by converting the transmitted serial data stream to the parallel data stream;

a clock signal generating device generating a clock signal and transmitting the clock signal to the P/S converter of the transmitting device for performing the first conversion operation, wherein the transmitting device further transmits the clock signal to the S/P converter of the receiving device for performing the second conversion operation, the first and second conversion operations being performed in a continuous and in-phase manner; and

a synchronizing device generating a synchronizing signal based on the clock signal and as a function of the first conversion operation of the P/S converter and providing the synchronizing signal to the S/P converter for synchronizing the second conversion operation of the S/P converter.

2. The data transfer device according to claim 1, wherein the P/S converter includes:

an input register clocked with the clock signal, the input register including a first parallel input for receiving the parallel data stream and a parallel output for transmitting a parallel output signal,

a shift register clocked with the clock signal, the shift register including a second parallel input for receiving the parallel output signal and a serial output for transmitting the serial data stream to the data transfer channel, and

an internal bus connecting the parallel output of the input register to the second parallel input of the shift register.

3. The data transfer device according to claim 2, wherein the synchronizing device includes a synchronizing frame generating device for generating and inserting a predetermined synchronizing frame into the serial data stream at the serial output of the shift register.

4. The data transfer device according to claim 1, wherein the S/P converter includes:

a shift register clocked with the clock signal, the shift register has a serial input receiving the serial data stream and a first parallel output for transmitting a parallel output signal,

an output register clocked with the clock signal, the output register includes a parallel input to receive the first parallel output signal of the shift register and a second parallel output for transmitting the parallel data stream, and

an internal bus connecting the first parallel output of the shift register to the parallel input of the output register.

5. The data transfer device according to claim 2, wherein the S/P converter includes:

a further shift register clocked with the clock signal, the further shift register has a serial input receiving the serial data stream and a further parallel output for transmitting a further parallel output signal,

an output register clocked with the clock signal, the output register includes a third parallel input receiving the further parallel output signal of the further shift register and a different parallel output for transmitting the parallel data stream, and

a further internal bus connecting the further parallel output of the further shift register to the third parallel input of the output register.

6. The data transfer device according to claim 5,

wherein each of a plurality of transfer frames has a predetermined format, the predetermined format including a start bit, a data word having a predetermined number of bits, a parity bit and a stop bit, and

wherein a length of the shift register and the further shift register corresponds to a length of the predetermined format.

7. The data transfer device according to claim 6,

wherein the synchronizing device includes a synchronizing frame recognition device for generating a predetermined synchronizing frame,

wherein the predetermined synchronizing frame has the predetermined format, and

wherein bits of the data word are set, and the parity bit does not correspond to a parity of the data word.

8. The data transfer device according to claim 6, wherein the P/S converter includes a parity generator connected to the internal bus and to the shift register for generating and providing the parity bit into the shift register, the parity bit corresponding to bits of the data word.

9. The data transfer device according to claim 6, wherein the S/P converter includes a parity generator connected to the further internal bus and to the output register for generating the parity bit and providing the parity bit as a load signal to the output register, the parity bit corresponding to bits of the data word.

10. The data transfer device according to claim 1, wherein the transmitter device includes a first device for changing a data word length of the parallel data stream and a second device for adjusting the synchronizing signal.

11. The data transfer device according to claim 1, wherein the receiving device includes a status check register for:

programming a data word length of the parallel data stream and a parity bit, and transmitting a status of the receiving device.

12. The data transfer device according to claim 1, wherein the receiving device includes an error memory device for storing faulty data transfers.

13. The data transfer device according to claim 1, further comprising:

a serial interface connecting the transmitting device to the receiving device for transmitting diagnostic functions.

14. The data transfer device according to claim 13, wherein the serial interface includes an SPI interface.

15. The data transfer device according to claim 1, wherein the transmitting device includes a microcontroller of a motor vehicle control unit, and wherein the receiving device includes an output stage IC of the motor vehicle control unit.

16. The data transfer device according to claim 1, further comprising a separate transmission path coupled between the transmitting device and the receiving device, wherein the synchronizing signal is transmittable via the separate transmission path from the transmitting device to the receiving device.

17. The data transfer device according to claim 1, further comprising another separate transmission path coupled between the transmitting device and the receiving device, wherein the clock signal is transmittable via the another separate transmission path from the transmitting device to the receiving device.

18. The data transfer device according to claim 1, further comprising:

a separate transmission path coupled between the transmitting device and the receiving device, wherein the synchronizing signal is transmittable via the separate transmission path from the transmitting device to the receiving device; and

another separate transmission path coupled between the transmitting device and the receiving device, wherein the clock signal is transmittable via the another separate transmission path from the transmitting device to the receiving device.

19. A data transfer device for unidirectionally and serially transferring data from a transmitting device to a receiving device, comprising:

a parallel-to-serial (P/S) converter provided in the transmitting device, the P/S converter performing a first conversion operation by converting a parallel data stream in the transmitting device to a serial data stream, the P/S converter transmitting the serial data stream to the receiving device via a data transfer channel, the serial data stream including transfer frames which have a predefined format, wherein the P/S converter includes;

an input register clocked with the clock signal, the input register including a first parallel input for receiving the parallel data stream and a parallel output for transmitting a parallel output signal;

a shift register clocked with the clock signal, the shift register including a second parallel input for receiving the parallel output signal and a serial output for transmitting the serial data stream to the data transfer channel; and

an internal bus connecting the parallel output of the input register to the second parallel input of the shift register;

a serial-to-parallel (S/P) converter provided in the receiving device, the S/P converter performing a second conversion operation by converting the transmitted serial data stream to the parallel data stream;

a clock signal generating device generating a clock signal and transmitting the clock signal to the P/S converter of the transmitting device for performing the first conversion operation, wherein the transmitting device further transmits the clock signal to the S/P converter of the receiving device for performing the second conversion operation, the first and second conversion operations being performed in a continuous and in-phase manner; and

a synchronizing device generating a synchronizing signal based on the clock signal and as a function of the first conversion operation of the P/S converter and providing the synchronizing signal to the S/P converter for synchronizing the second conversion operation of the S/P converter;

wherein the synchronizing device includes a decrementer clocked with the clock signal and generating a synchronizing pulse signal after a preselected decrementing cycle; and

wherein the shift register is controlled using the synchronizing pulse for receiving the parallel output signal of the input register transmitted via the internal bus.

20. A data transfer device for unidirectionally and serially transferring data from a transmitting device to a receiving device, comprising:

a parallel-to-serial (P/S) converter provided in the transmitting device, the P/S converter performing a first conversion operation by converting a parallel data stream in the transmitting device to a serial data stream, the P/S converter transmitting the serial data stream to the receiving device via a data transfer channel, the serial data stream including transfer frames which have a predefined format;

a serial-to-parallel (S/P) converter provided in the receiving device, the S/P converter performing a second conversion operation by converting the transmitted serial data stream to the parallel data stream wherein the S/P converter includes;

a shift register clocked with the clock signal, the shift register has a serial input receiving the serial data stream and a first parallel output for transmitting a parallel output signal;

an output register clocked with the clock signal, the output register includes a parallel input to receive the first parallel output signal of the shift register and a second parallel output for transmitting the parallel data stream; and

an internal bus connecting the first parallel output of the shift register to the parallel input of the output register;

a clock signal generating device generating a clock signal and transmitting the clock signal to the P/S converter of the transmitting device for performing the first conversion operation, wherein the transmitting device further transmits the clock signal to the S/P converter of the receiving device for performing the second conversion operation, the first and second conversion operations being performed in a continuous and in-phase manner; and

a synchronizing device generating a synchronizing signal based on the clock signal and as a function of the first conversion operation of the P/S converter and providing the synchronizing signal to the S/P converter for synchronizing the second conversion operation of the S/P converter, wherein the synchronizing device includes a decrementer clocked with the clock signal, the decremeter generating a synchronizing pulse after a predetermined decrementing cycle; and

wherein the output register is controlled using the synchronizing pulse for receiving the parallel output signal of the shift register transmitted over the internal bus.

21. A data transfer device for unidirectionally and serially transferring data from a transmitting device to a receiving device, comprising:

a parallel-to-serial (P/S) converter provided in the transmitting device, the P/S converter performing a first conversion operation by converting a parallel data stream in the transmitting device to a serial data stream, the P/S converter transmitting the serial data stream to the receiving device via a data transfer channel, the serial data stream including transfer frames which have a predefined format, wherein the P/S converter includes;

an input resister clocked with the clock signal, the input register including a first parallel input for receiving the parallel data stream and a parallel output for transmitting a parallel output signal;

a shift resister clocked with the clock signal, the shift register including a second parallel input for receiving the parallel output signal and a serial output for transmitting the serial data stream to the data transfer channel; and

an internal bus connecting the parallel output of the input register to the second parallel input of the shift register;

a serial-to-parallel (S/P) converter provided in the receiving device, the S/P converter performing a second conversion operation by converting the transmitted serial data stream to the parallel data stream, wherein the S/P converter includes;

a further shift register clocked with the clock signal, the further shift register has a serial input receiving the serial data stream and a further parallel output for transmitting a further parallel output signal;

an output register clocked with the clock signal, the output register includes a third parallel input receiving the further parallel output signal of the further shift register and a different parallel output for transmitting the parallel data stream; and

a further internal bus connecting the further parallel output of the further shift register to the third parallel input of the output register;

a clock signal generating device generating a clock signal and transmitting the clock signal to the P/S converter of the transmitting device for performing the first conversion operation, wherein the transmitting device further transmits the clock signal to the S/P converter of the receiving device for performing the second conversion operation, the first and second conversion operations being performed in a continuous and in-phase manner; and

a synchronizing device generating a synchronizing signal based on the clock signal and as a function of the first conversion operation of the P/S converter and providing the synchronizing signal to the S/P converter for synchronizing the second conversion operation of the S/P converter, wherein the synchronizing device includes a decrementer clocked with the clock signal, the decremeter generating a synchronizing pulse after a predetermined decrementing cycle; and

wherein the output register is controlled using the synchronizing pulse for receiving the further parallel output signal of the further shift register transmitted via the further internal bus.

22. A data transfer device for unidirectionally and serially transferring data from a transmitting device to a receiving device, comprising:

a parallel-to-serial (P/S) converter provided in the transmitting device, the P/S converter performing a first conversion operation by converting a parallel data stream in the transmitting device to a serial data stream, the P/S converter transmitting the serial data stream to the receiving device via a data transfer channel, the serial data stream including transfer frames which have a predefined format wherein the P/S converter includes;

an input register clocked with the clock signal, the input register including a first parallel input for receiving the parallel data stream and a parallel output for transmitting a parallel output signal;

a shift register clocked with the clock signal, the shift register including a second parallel input for receiving the parallel output signal and a serial output for transmitting the serial data stream to the data transfer channel; and

an internal bus connecting the parallel output of the input resister to the second parallel input of the shift register;

a serial-to-parallel (S/P) converter provided in the receiving device, the S/P converter performing a second conversion operation by converting the transmitted serial data stream to the parallel data stream, wherein the S/P converter includes;

a further shift register clocked with the clock signal, the further shift register has a serial input receiving the serial data stream and a further parallel output for transmitting a further parallel output signal;

an output register clocked with the clock signal, the output register includes a third parallel input receiving the further parallel output signal of the further shift register and a different parallel output for transmitting the parallel data stream; and

a further internal bus connecting the further parallel output of the further shift register to the third parallel input of the output register;

a clock signal generating device generating a clock signal and transmitting the clock signal to the P/S converter of the transmitting device for performing the first conversion operation, wherein the transmitting device further transmits the clock signal to the S/P converter of the receiving device for performing the second conversion operation, the first and second conversion operations being performed in a continuous and in-phase manner; and

a synchronizing device generating a synchronizing signal based on the clock signal and as a function of the first conversion operation of the P/S converter and providing the synchronizing signal to the S/P converter for synchronizing the second conversion operation of the S/P converter, wherein the synchronizing device includes a first synchronizing frame recognition device for generating and inserting a predetermined synchronizing frame into the serial data stream at the serial output of the shift register;

wherein the S/P converter includes a second synchronizing frame recognition device for recognizing the predetermined synchronizing frame in the further shift register; and

wherein the output register is controlled using at least one of the first and second synchronizing frame recognition devices for receiving the further parallel output signal of the further shift register transmitted via the further internal bus.

23. A data transfer device for unidirectionally and serially transferring data from a transmitting device to a receiving device, comprising:

a parallel-to-serial converter provided in the transmitting device, the parallel-to-serial converter performing a first conversion operation by converting a parallel data stream in the transmitting device to a serial data stream, the parallel-to-serial converter transmitting the serial data stream to the receiving device via a data transfer channel, the serial data stream including transfer frames having a predefined format;

a serial-to-parallel converter provided in the receiving device, the serial-to-parallel converter performing a second conversion operation by converting the transmitted serial data stream to the parallel data stream;

means for generating a clock signal and transmitting the clock signal to the parallel-to-serial converter and to the serial-to-parallel converter for performing the first conversion operation and the second conversion operation in an in-phase manner;

means for generating a synchronizing signal based on the first conversion operation of the parallel-to-serial converter; and

means for transmitting the synchronizing signal to the serial-to-parallel converter for synchronizing the second conversion operation of the serial-to-parallel converter.

24. A data transfer system for unidirectionally and serially transferring data, the system comprising:

a clock line for providing a clock signal;

a reset line for providing a reset signal;

a serial data line;

a transmitting arrangement including;

a parity generator arrangement for generating parity data;

a shift register arrangement being coupled to the clock line and the reset line, and being coupled to the parity generator arrangement for receiving the parity data, the shift register arrangement using the serial data line to output serial data;

an input register arrangement for receiving parallel data from a microcontroller, the input register arrangement being coupled to the clock line, the reset line, the parity generator arrangement and the shift register arrangement, wherein the shift register arrangement outputs the serial data based on the parallel data and the parity data; and

a synchronizing arrangement being coupled to the clock line and the reset line for providing a synchronizing signal, and being coupled to the shift register arrangement for providing the synchronizing signal thereto, wherein the synchronizing arrangement is a decrementer arrangement; and

a receiving arrangement coupled to the transmitting arrangement, the receiving arrangement including;

another parity generator arrangement for generating another parity data;

another shift register arrangement coupled to the clock line, the reset line and the serial data line, and coupled to the another parity generator arrangement for receiving the another parity data, the another shift register arrangement converting the serial data line to another parallel data; and

an output register arrangement for receiving the another parallel data from the another shift register arrangement, the output register arrangement being coupled to the clock line, the reset line, the another parity generator arrangement, the synchronizing arrangement and the another shift register arrangement, wherein the output register arrangement outputs the parallel data based on the another parallel data, the another parity data and the synchronization signal.