Two-level mini-block storage system for volume data sets
First Claim
1. A method for arranging voxel data in DRAM memory modules to avoid idle cycles during data transfer in a volume rendering system, thereby permitting real time volume rendering by data transfer at the maximum burst rate of the DRAM memory modules, comprising the steps of:
- arranging voxel data from a volume data set into mini-blocks;
providing a number of DRAM modules each having a number of DRAM memory banks; and
, within each DRAM module, assigning mini-blocks to the memory banks thereof so that consecutively accessed mini-blocks are assigned to different banks within the associated DRAM module, said mini-blocks being assigned both to a specific DRAM and a specific bank within a DRAM in a two-level storage system, such that upon consecutive accessing of said banks, idle cycles during data transfer from the associated DRAM module are avoided.
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Abstract
A two-level skewing architecture is imposed on the memory subsystem of a volume rendering system in which voxel data is stored in mini-blocks assigned to a set of DRAM memory modules, thereby permitting data transfer at the maximum burst rate of the DRAM memory and enabling real-time volume rendering. Within each DRAM module, mini-blocks are assigned to the memory banks so that consecutively accessed mini-blocks are assigned to different banks, thereby avoiding idle cycles during data transfer and increasing DRAM transfer efficiency to nearly 100%. In one embodiment, read-out of voxel data from banks of the DRAM memory proceeds from left to right unless there is a conflict of banks, in which case the read-out order is reversed. A specialized de-skewing network is provided to re-order the voxel data read out from DRAM memory so that the voxels can be processed in the order which they are arranged in the volume data set rather than the order in which they are stored in memory.
71 Citations
7 Claims
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1. A method for arranging voxel data in DRAM memory modules to avoid idle cycles during data transfer in a volume rendering system, thereby permitting real time volume rendering by data transfer at the maximum burst rate of the DRAM memory modules, comprising the steps of:
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arranging voxel data from a volume data set into mini-blocks;
providing a number of DRAM modules each having a number of DRAM memory banks; and
,within each DRAM module, assigning mini-blocks to the memory banks thereof so that consecutively accessed mini-blocks are assigned to different banks within the associated DRAM module, said mini-blocks being assigned both to a specific DRAM and a specific bank within a DRAM in a two-level storage system, such that upon consecutive accessing of said banks, idle cycles during data transfer from the associated DRAM module are avoided. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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7. The method of claim 6, wherein a mini-block with coordinates (Xmb, Ymb, Zmb) is assigned to a bank in accordance with the following formula
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X mb M ⌋ + ⌊ Y mb M ⌋ + ⌊ Z mb M ⌋ ) mod B , where M is the number of independent memory chips and B is the number of banks per chip, and where B is the number of banks per DRAM chip.
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Specification
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- Resources
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Current AssigneeTeraRecon Inc. (Fortive Corp.)
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Original AssigneeTeraRecon Inc. (Fortive Corp.)
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InventorsCorrell, Kenneth, Peet, William, Knittel, James
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Primary Examiner(s)Kim, Matthew
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Assistant Examiner(s)TZENG, FRED
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Application NumberUS09/191,865Time in Patent Office985 DaysField of Search711/5, 711/104, 711/157, 345/424, 345/505, 600/410, 623/22.3US Class Current711/5CPC Class CodesG06T 1/60 Memory managementG06T 15/005 General purpose rendering a...G06T 15/08 Volume rendering
