Method and apparatus for efficient software updating

• US 6,266,736 B1
• Filed: 01/31/1997
• Issued: 07/24/2001
• Est. Priority Date: 01/31/1997
• Status: Expired due to Fees

• Current Assignee: Rockwell Collins, Inc. (Raytheon Technologies Corporation d/b/a RTX)
• Original Assignee: Sony Transcom Incorporated (Rockwell International Corporation), Sony Corporation (Sony Group Corp.)
• Inventors: Atkinson, Michael R., Auerbach, Russell
• Primary Examiner(s): COURTENAY III, ST JOHN
• Application Number:
  US08/791,933
• Time in Patent Office: 1,635 Days
• Field of Search: 395/430, 395/712, 395/619, 711/103, 711/148, 717/11
• US Class Current: 711/103
• CPC Class Codes: G06F 8/656 while running

Abstract

A method to update information including code and data in a non-volatile memory reliably and efficiently to avoid loss of information during the loading process and to minimize aircraft service downtime in an In-Flight Entertainment System (IFES). The non-volatile memory is partitioned into two sections: one section contains the currently valid information and the other is available for loading the new information. A section pointer is used to keep track of the currently valid section and to select the loading section. The new information is loaded to the selected loading section. A validation procedure is performed to determine if the loading is successful. When the loading of the new information is successfully completed, the section pointer is updated to point to the newly loaded section.

Claims

1. In an In-Flight Entertainment System (IFES) having a processor coupled to a non-volatile memory, a method for loading new information into the non-volatile memory in order to replace a current information, the method comprising:

partitioning the non-volatile memory into at least two sections, a first section of the at least two sections containing the current information;

maintaining a section pointer for use by the processor for accessing the non-volatile memory and selecting a second section of the at least two sections, the second section not containing the current information;

loading the new information into the second section of the at least two sections as indicated by the maintained section pointer;

validating the new information after it is loaded into the second section;

updating the section pointer to indicate that current information is stored in the second section after the loaded new information is validated, wherein the section of the first and second sections not containing the current information is used for loading subsequent new information to replace the current information.

2. The method as set forth in claim 1, wherein the at least two sections are addressed by the processor using a common address, the section pointer utilized to enable a section of the at least two sections to be accessed by the processor.

3. The method as set forth in claim 1, wherein loading further comprises:

determining if a random access memory (RAM) flag is set, the RAM flag indicating that new information has been transferred to a RAM; and

if the RAM flag is set,

determining if the new information is ready to be loaded, and

loading the new information into the second section if the new information is ready to be loaded, and if the RAM flag is not set, transferring the new information from the non-volatile memory to the RAM.

4. The method as set forth in claim 1, further comprising:

compressing the new information prior to loading; and

decompressing the compressed information to produce decompressed information and transferring the decompressed information to a RAM for access by the processor.

5. The method as set forth in claim 1, wherein validating comprises checking for a checksum error.

6. An in flight entertainment system (IFES) comprising:

a processor;

a non-volatile memory coupled to the processor, said non-volatile memory partitioned into at least two sections;

a section pointer coupled to the non-volatile memory and the processor, said section pointer for use by the processor for accessing the first non-volatile memory and selecting a second section of the at least two section, said second section not containing the current information;

said processor configured to control the loading of new information into the non-volatile memory in order to replace a current information in order to decrease aircraft service downtime by loading the new information into the second section of the at least two sections as indicated by the maintained section pointer, validating said new information after it is loaded into the second section, and updating said section pointer to indicate that current information is stored in the second section after said loaded new information is validated, wherein the section of the first and second sections not containing the current information is used for loading subsequent new information to replace the current information.

7. The system as set forth in claim 6 wherein the at least two sections are addressed by the processor using a common address, said section pointer utilized to enable a section of the at least two sections to be accessed by the processor.

8. The system as set forth in claim 6, wherein the processor is configured to load by;

determining if a random access memory (RAM) flag is set, the RAM flag indicating that new information has been transferred to a RAM; and

if the RAM flag is set,

determining if the new information is ready to be loaded, and

loading the new information into the second section if the new information is ready to be loaded, and

if the RAM flag is not set, transferring the new information from the first non-volatile memory to the RAM.

9. The system as set forth in claim 6, wherein the processor is further configured to:

compress the new information prior to loading; and

decompress the compressed information to produce decompressed information and transferring the decompressed information to a RAM for access by the processor.

10. The system as set forth in claim 6, wherein the at least two sections are stored in a single non-volatile memory device.

11. The system as set forth in claim 6, wherein the at least two sections are stored in a plurality of separate non-volatile memory devices.