Intermediate-grain reconfigurable processing device
First Claim
1. A programmable integrated circuit comprising:
- logic units which perform operations on data in response to instructions of a defined set of instructions;
memories which store and retrieve data in response to received addresses;
a configurable interconnect which provides signal transmission between the logic units and memories, the interconnect being configurable from configuration control data to define data paths, originating at logic units and/or memories, through the interconnect as address inputs to memories, data inputs to memories and logic units, and instruction inputs to logic units such that the interconnect is configurable to operate on data addresses or instructions; and
programmable configuration storage for storing the configuration control data.
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Abstract
A programmable integrated circuit utilizes a large number of intermediate-grain processing elements which are multibit processing units arranged in a configurable mesh. The coarse-grain resources, such as memory and processing, are deployable in a way that takes advantage of the opportunities for optimization present in given problems. To accomplish this, the interconnect supports three different modes of operation: a static value in which a value set by the configuration data is provided to a functional unit, static source in which another functional unit serves as the value source, and a dynamic source mode in which the source is determined by the value from another functional unit.
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Citations
30 Claims
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1. A programmable integrated circuit comprising:
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logic units which perform operations on data in response to instructions of a defined set of instructions;
memories which store and retrieve data in response to received addresses;
a configurable interconnect which provides signal transmission between the logic units and memories, the interconnect being configurable from configuration control data to define data paths, originating at logic units and/or memories, through the interconnect as address inputs to memories, data inputs to memories and logic units, and instruction inputs to logic units such that the interconnect is configurable to operate on data addresses or instructions; and
programmable configuration storage for storing the configuration control data. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A programmable integrated circuit comprising:
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logic units which perform operations on data in response to instructions of a defined set of instructions;
memories which store and retrieve data in response to received addresses;
a configurable interconnect which provides signal transmission between the logic units and memories, the interconnect being configurable from configuration control data to define data paths through the interconnect as address inputs to memories, data inputs to memories and logic units, and instruction inputs to logic units such that the interconnect is configurable to operate on data addresses or instructions; and
programmable configuration storage for storing the configuration control data;
wherein a global context selection signal that selects among multiple contexts is globally broadcast to the programmable configuration storage of the device.
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9. A programmable integrated circuit comprising:
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logic units which perform operations on data in response to instructions of a defined set of instructions and which are configurable to be chained together to form wider data paths than provided by a single logic unit;
memories which store and retrieve data in response to received addresses;
a configurable interconnect which provides signal transmission between the logic units and memories, the interconnect being configurable from configuration control data to define data paths through the interconnect as address inputs to memories, data inputs to memories and logic units, and instruction inputs to logic units; and
programmable configuration storage for storing the configuration control data.
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10. A programmable integrated circuit comprising:
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logic units which perform operations on data in response to instructions of a defined set of instructions;
memories which store and retrieve data in response to received addresses;
a configurable interconnect which provides signal transmission between the logic units and memories, the interconnect being configurable from configuration control data to define data paths through the interconnect as address inputs to memories, data inputs to memories and logic units, and instruction inputs to logic units such that the interconnect is configurable, the interconnect being configurable to provide a value to a logic unit or memory from a source, which is determined by a value from another logic unit or memory; and
programmable configuration storage for storing the configuration control data.
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11. A programmable integrated circuit comprising:
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logic units which perform operations on data in response to instructions of a defined set of instructions;
memories which store and retrieve data in response to received addresses, the logic units being each grouped with memories to form repeating functional units;
a configurable interconnect which provides signal transmission between the logic units and memories, the interconnect being configurable from configuration control data to define data paths through the interconnect as address inputs to memories, data inputs to memories and logic units, and instruction inputs to logic units such that the interconnect is configurable to operate on data, addresses or instructions; and
programmable configuration storage for storing the configuration control data. - View Dependent Claims (12, 13, 14)
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15. An integrated reconfigurable computing device, comprising:
- an array of functional units comprising;
multibit arithmetic logic units which perform operations on data in response to instructions;
memories which store and retrieve data in response to received addresses;
function switches which determine the source of the instructions to the logic units; and
switches which are configurable by the other functional units and determine the source of addresses to the memories and the source of data to the logic units and memories. - View Dependent Claims (16, 17, 18, 19, 20, 21)
- an array of functional units comprising;
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22. A method for organizing signal transmission within an array of logic units which perform operations on data in response to instructions and memories which store and retrieve data in response to received addresses, the method comprising:
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transmitting data read from the memories as data to the logic units or addresses or data to other memories;
transmitting data generated by the logic units as data to other logic units or addresses or data to the memories; and
transmitting data from logic units or memories as control to other logic units or memories. - View Dependent Claims (23, 24, 25, 26, 27, 28, 29, 30)
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Specification