Deep trace memory system for a protocol analyzer
DCFirst Claim
1. A protocol analyzer having a deep trace memory system that stores traces captured from a communication interface for presentation by a host processor, the protocol analyzer comprising:
- a portable chassis physically separate from the host processor that includes;
a host port that provides a connection to the host processor;
an interface port that provides a connection to the communication interface;
a trace buffer memory;
logic circuitry that controls selective write operations of traces from the interface port to the trace buffer and selective read operations of traces from the trace buffer to the host port in response to parameters directed by the host processor; and
a hardware search engine that locates specified data patterns as directed by the host processor within the trace buffer.
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Abstract
A deep trace buffer management system for a protocol analyzer includes a hardware search engine that locates specified data patterns within the trace buffer as directed by a host processor. The protocol analyzer is preferably connected to a laptop computer that serves as the host processor, and the protocol analyzer preferably is housed in a portable chassis separate from the host processor and has a host port to connect to the host processor through a relatively small bandwidth port. An interface port connects the protocol analyzer to the communication interface under analysis. Logic circuitry controls selective read and write operations of traces to and from the trace buffer in response to parameters as directed by the host processor.
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Citations
21 Claims
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1. A protocol analyzer having a deep trace memory system that stores traces captured from a communication interface for presentation by a host processor, the protocol analyzer comprising:
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a portable chassis physically separate from the host processor that includes;
a host port that provides a connection to the host processor;
an interface port that provides a connection to the communication interface;
a trace buffer memory;
logic circuitry that controls selective write operations of traces from the interface port to the trace buffer and selective read operations of traces from the trace buffer to the host port in response to parameters directed by the host processor; and
a hardware search engine that locates specified data patterns as directed by the host processor within the trace buffer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
a dual port memory connected the interface port and the trace buffer to serve as a first-in, first out (fifo) buffer;
addressing circuitry connected to the dual port memory and the trace buffer having a write address counter, a read address counter and an address full counter; and
decision circuitry connected to the addressing circuitry and the dual port memory to analyze data in the fifo buffer and determine whether the data in the fifo buffer is a trace to be stored in the trace buffer.
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10. The protocol analyzer of claim 1 wherein the hardware search engine comprises:
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a pattern memory loaded with a desired data pattern;
an address counter containing an address in the trace buffer to initiate; and
a comparator connected to the pattern memory and the trace buffer.
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11. A system for analyzing a communication interface comprising:
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a host processor that includes;
a user interface;
a computer processor; and
a main memory;
a protocol analyzer distinct from the host processor that includes;
a host port that provides a connection to the host processor;
an interface port that provides a connection to the communication interface;
a trace buffer memory;
logic circuitry that controls selective write operations of traces from the interface port to the trace buffer and selective read operations of traces from the trace buffer to the host port in response to parameters as directed by the host processor; and
a hardware search engine that locates specified data patterns as directed by the host processor within the trace buffer. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
a dual port memory connected the interface port and the trace buffer to serve as a first-in, first out (fifo) buffer;
addressing circuitry connected to the dual port memory and the trace buffer having a write address counter, a read address counter and an address full counter; and
decision circuitry connected to the addressing circuitry and the dual port memory to analyze data in the fifo buffer and determine whether the data in the fifo buffer is a trace to be stored in the trace buffer.
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20. The system of claim 11 wherein the hardware search engine comprises:
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a pattern memory loaded with a desired data pattern;
an address counter containing an address in the trace buffer to initiate; and
a comparator connected to the pattern memory and the trace buffer.
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21. A method of managing memory of a deep trace buffer of a protocol analyzer for a communication interface comprising:
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(a) selectively writing traces from the communication interface into the trace buffer of the protocol analyzer;
(b) using a hardware search engine in the protocol analyzer to identify portions of the traces in the trace buffer matching a specified data pattern as determined by a host processor having a computer processor and a main memory separate from the trace buffer of the protocol analyzer; and
(c) in response to step (b), selectively reading at least a portion of the traces from the buffer to the host processor.
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Specification