Data transfer network on a computer chip using a re-configurable path multiple ring topology

• US 6,266,797 B1
• Filed: 11/14/1997
• Issued: 07/24/2001
• Est. Priority Date: 01/16/1997
• Status: Expired due to Term

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Hartmann, Alfred C., Godfrey, Gary M.
• Primary Examiner(s): Smith, Matthew S.
• Assistant Examiner(s): Siek, Vuthe
• Application Number:
  US08/970,691
• Time in Patent Office: 1,348 Days
• Field of Search: 395/500.46, 395/500.45, 395/200.81, 395/822.83, 395/280, 395/306, 710/116, 710/126, 710/129, 710/100, 710/131, 703/24, 703/25, 709/251, 716/12, 716/13, 716/14, 716/1
• US Class Current: 710/10
• CPC Class Codes: G06F 15/78 comprising a single central processing unit
• CPC Class Codes: G06F 15/8015 One dimensional arrays, e.g. rings, linear arrays, buses
• CPC Class Codes: H04L 12/42 Loop networks
• CPC Class Codes: H04L 69/08 Protocols for interworking; Protocol conversion
• CPC Class Codes: H04L 9/40 Network security protocols

Abstract

A computer chip including a data transfer network. The data transfer network comprises a plurality of communication ports and a plurality of modules. Each of the communication ports is directly connected to two or more other communication ports, and each of the communication ports is operable to communicate data. Each of the plurality of modules is coupled to at least one of the plurality of communication ports, and the plurality of modules are operable to communicate with each other through the communication ports. Furthermore, the plurality of communication ports are dynamically configurable to form two or more separate communication paths. The plurality of communication ports may be bi-directionally coupled and operable to communicate data with each other. The plurality of communication ports may also be dynamically configurable to form two or more communication rings. A first plurality of communication ports preferably comprise a first communication path, and a second plurality of communication ports comprise a second communication path. A first communication port in the first communication path is connected between two communication ports in the second communication path. The first communication port is then operable to transfer data between the two communication ports in the second communication path. The first plurality of communication ports and the second plurality of communication ports are also dynamically re-configurable to form two or more communication paths. The first plurality of communication ports and the second plurality of communication ports are preferably dynamically re-configurable to form one or more communication rings.

Claims

1. A single monolithic computer chip comprising a data transfer network, the computer chip comprising:

a plurality of communication ports comprised on said single monolithic computer chip, wherein each of said communication ports are directly connected to two or more other communication ports to form two or more communications paths, wherein each of said communication ports are operable to communicate data, wherein said two or more communication paths comprise intra-chip communication paths; and

a plurality of modules comprised on said single monolithic computer chip, wherein each of said plurality of modules is coupled to at least one of said plurality of communication ports, and wherein said plurality of modules comprise one or more of a processor, an I/O controller, a memory, or a task specific hybrid integrated circuit;

wherein the single monolithic computer chip is dynamically configurable to form a first communication path between a first communication port and a second communication port during a first time period and is dynamically configurable to form a second communication path between the first communication port and a third communication port during a second time period, wherein said first communication path and said second communication path comprise intra-chip communication paths.

2. The single monolithic computer chip of claim 1, further comprising:

a plurality of buses comprised on said computer chip and coupled between said plurality of communications ports;

wherein said plurality of ports are operable to dynamically select different ones of said buses to dynamically form said communication paths.

3. The single monolithic computer chip of claim 2, wherein each of said communication ports includes configuration logic for dynamically configuring said buses to form said first communication path in said first instance and said second different communication path in said second instance.

4. The single monolithic computer chip of claim 3,

wherein said first communication path and said second different communication path are coupled to each other to allow communication ports connected to said first communication path to communicate data to communication ports connected to said second different communication path.

5. The single monolithic computer chip of claim 2, wherein a first bus included in said plurality of buses comprises an address line and a control line.

6. The single monolithic computer chip of claim 1,

wherein said plurality of communication ports are bi-directionally coupled and are operable to communicate data with each other.

7. The single monolithic computer chip of claim 6, wherein said plurality of communication ports are dynamically configurable to form two or more isolated communication rings.

8. The single monolithic computer chip of claim 7, wherein the plurality of communication ports include a first plurality of communication ports and a second plurality of communication ports, wherein the first plurality of communication ports comprise said first communication path, and wherein the second plurality of communication ports comprise said second different communication path;

wherein at least one of the first plurality of communication ports comprised in said first communication path is connected between two communication ports in said second communication path;

wherein said at least one of the first plurality of communication ports is operable to transfer data between said two communication ports in said second communication path; and

wherein said first and second pluralities of communication ports are re-configurable to form different communication paths.

9. The single monolithic computer chip of claim 6, wherein each communication port in a communication path is operable to perform bi-directional communications with every other communication port in said communication path.

10. The single monolithic computer chip of claim 1,

wherein the plurality of communication ports include a first plurality of communication ports and a second plurality of communication ports, wherein the first plurality of communication ports comprise said first communication path, and wherein the second plurality of communication ports comprise said second different communication path;

wherein one of said first plurality of communication ports is operable to communicate to with one of said second plurality of communication ports.

11. The single monolithic computer chip of claim 1, wherein said plurality of communication ports comprises a first plurality of communication ports and a second plurality of communication ports;

wherein said first plurality of communication ports are directly electrically coupled, and wherein said second plurality of communication ports are directly electrically coupled;

wherein said first plurality of communication ports includes a first communication port and a last communication port, and wherein said second plurality of communication ports includes a first communication port and a last communication port;

wherein said first communication port of said first plurality of communication ports is coupled to said first communication port of said second plurality of communication ports, and wherein said last communication port of said first plurality of communication ports is coupled to said last communication port of said second plurality of communication ports.

12. The single monolithic computer chip of claim 1, wherein a first communication port included in said plurality of communication ports is configured to be included in more than one said communication paths concurrently.

13. A single monolithic computer chip comprising a data transfer network, the computer chip comprising:

a first plurality M of communication ports comprised on said single monolithic computer chip, wherein said first plurality of communication ports are directly coupled and are operable to communicate data with each other; and

a second plurality N of communication ports comprised on said single monolithic computer chip, wherein said second plurality of communication ports are directly coupled and are operable to communicate data with each other;

a plurality of modules comprised on said single monolithic computer chip, wherein each of said plurality of modules is coupled to at least one of said plurality of communication ports; and

wherein said plurality of modules comprise one or more of a processor, an I/O controller, a memory, or a task specific hybrid integrated circuit;

wherein each of said first plurality M of communication ports is coupled to a corresponding one of said second plurality N of communication ports;

wherein the single monolithic computer chip is dynamically configurable to form a first communication path between a first subset of the first plurality M of communication ports and a first subset of the second plurality N of communication ports during a first time period and is dynamically configurable to form a second communication path between the first subset of the first plurality M of communication ports and a second subset of the second plurality N of communication ports during a second time period, wherein said first communication path and said second communication path comprise intra-chip communication paths.

14. The single monolithic computer chip of claim 13,

wherein said first plurality M of communication ports are bi-directionally coupled and are operable to communicate data with each other;

wherein said second plurality N of communication ports are bi-directionally coupled and are operable to communicate data with each other.

15. The single monolithic computer chip of claim 14, wherein said first plurality M of communication ports and said second plurality N of communication ports are dynamically re-configurable to form one or more isolated communication rings.