Electrical mask identification of memory modules

• US 6,268,228 B1
• Filed: 01/27/1999
• Issued: 07/31/2001
• Est. Priority Date: 01/27/1999
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Hedberg, Erik L., Eustis, Steven M., Thoma, Endre P., DeForge, John B., Douse, David E., Litten, Susan M.
• Primary Examiner(s): Fourson, George
• Assistant Examiner(s): MANDALA, MICHELLE
• Application Number:
  US09/238,874
• Time in Patent Office: 916 Days
• Field of Search: 438/18, 438/131, 438/132, 438/618, 438/622, 438/FOR.142, 438/600, 438/601
• US Class Current: 438/18
• CPC Class Codes: G03F 7/70541 Tagging, i.e. hardware or software tagging of features or components, e.g. using tagging scripts or tagging identifier codes for identification of chips, shots or wafers

Abstract

Mask programmable conductors of the same construction as the mask layers they define are utilized for mask vintage identification. When the actual mask layer is altered, the change is recorded within the mask itself.

Mask identification can be fabricated to identify the following type of mask layers: DT—deep trench; SS—surface strap; DIFF—Diffusion; NDIFF—N Diffusion; PDIFF—P Diffusion; WL—N wells; PC—polysilicon gates; BN—N diffusion Implant; BP—P diffusion Implant; C1—first contact; M1—first metal layer; C2—second contact; and, M2—second metal layer.

Conducting paths that incorporate, in series, the mask programmable conductor technology devices are: M1-C1-PC-C1-DIFF-C1-M1-C2-M2; M1-C1-PDIFF-SS-DT-SS-PDIFF-C1-M1-C2-M2; M2-C2-M1-C1-PC-C1-M1; M2-C2-M1-C1-NDIFF-WL-NDIFF-C1-M1; and, M2-C2-M1-C1-NDIFF-C1-M1-C1-PC-C1-M1. These conducting paths are electrically opened with the omission of any of the layers in the series path.

Claims

1. A method for identifying design characteristics of a semiconductor device, comprising the steps of:

a) providing said semiconductor device having a plurality of semiconductor levels each having different mask layers;

b) forming electrical devices from each of said mask layers within each of said semiconductor levels, such that the make-up of said electrical devices is restricted to each technology of said mask layers; and

,

c) permanently encoding each of said electrical devices during fabrication of said semiconductor levels in a binary encoded format to identify said design characteristics.

2. The method of claim 1, wherein said step (b), forming electrical devices from each of said mask layers within each of said semiconductor levels, comprises forming conduction paths during fabrication of said semiconductor levels made from said different mask layers.

3. The method of claim 1, further comprising the step of:

d) electrically interrogating said semiconductor device for said design characteristics by reading the binary encoded electrical devices.

4. The method of claim 1, wherein said electrical devices further comprise mask programmable conductors.

5. The method of claim 1, wherein said step (c), encoding said electrical devices in a binary format, comprises changing said conduction paths during fabrication of said semiconductor levels such that electrical opens and shorts in said conduction paths provide the permanent binary encoded format for identifying said design characteristics.

10. The method of claim 1, wherein said step (b), forming electrical devices from each of said mask layers, comprises forming fusible-link structures during fabrication of said semiconductor levels.

6. A method for identifying mask vintage of a semiconductor device, comprising:

a) providing a semiconductor substrate having a plurality of semiconductor layers with different mask layer technologies;

b) fabricating at least one conductor for each of said plurality of mask layers using said mask layer technology of each layer;

c) encoding each of said at least one conductors in a binary encoded format to identify said mask vintage during fabrication; and

,

d) electrically interrogating said semiconductor device for said mask vintage by reading the binary encoded conductors.

11. The method of claim 6, wherein said step (b), fabricating at least one conductor, comprises fabricating at least one fusible-link structure using said mask layer technology of each layer.

7. A method for identifying mask vintage of a trench and surface strap structure on a semiconductor device, comprising:

a) providing a semiconductor substrate having a plurality of different mask layers;

b) forming a conduction path of conductors for each layer of said trench and surface strap structure, wherein each of said conductors is fabricated from one of said mask layers of said structure, said conduction path comprising;

1) connecting electrically conductive surface strap conductors on adjacent sides of said trench;

2) forming diffusion conductors for attachment to each of said surface strap conductors;

3) forming a first contact to each of said diffusion conductors;

4) electrically connecting non-contiguous first metal layer conductors to each of said first contacts;

5) forming a second contact to one of said first metal layer conductors; and

;

6) forming a second metal layer conductor for electrical connection to said second contact;

c) permanently encoding each said conduction path in a binary encoded format during fabrication of said semiconductor layers to identify said mask vintage; and

,

d) electrically interrogating said semiconductor device for said mask vintage by reading the binary encoded conduction path.

8. The method of claim 7 wherein said surface strap conductors and said first contacts are separated by a PFET transistor.

9. The method of claim 8 wherein said trench structure is connected to drain and source ports of a PFET transistor.

12. The method of claim 7, wherein said step (b), forming a conduction path of conductors, comprises forming fusible-link structures using said mask layer technology of each layer.