Microprocessor having air as a dielectric and encapsulated lines and process for manufacture

• US 6,268,261 B1
• Filed: 11/03/1998
• Issued: 07/31/2001
• Est. Priority Date: 11/03/1998
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Petrarca, Kevin S., Mih, Rebecca D.
• Primary Examiner(s): Elms, Richard
• Assistant Examiner(s): Pyonin, Adam
• Application Number:
  US09/185,185
• Time in Patent Office: 1,001 Days
• Field of Search: 438/422, 438/421, 438/619, 438/622, 438/411, 438/412, 438/461
• US Class Current: 438/421
• CPC Class Codes: H01L 21/764 Air gaps H01L21/76264 takes precedence
• CPC Class Codes: H01L 21/7682 the dielectric comprising air gaps

Abstract

A process for manufacturing a semiconductor circuit. The process comprises creating a plurality of adjacent conductive lines having a solid fill between the conductive lines; creating one or more layers above the lines and the fill; creating one or more pathways to the fill through the layers; and converting the fill to a gas that escapes through the pathways, leaving an air void between adjacent lines. To protect the lines from oxidation during processing, a related process for encapsulating conductive lines in one or more adhesion-promotion barrier layers may be performed. The encapsulation process may also be practiced in conjunction with other semiconductor manufacturing processes. The processes result in a multi-layer semiconductor circuit comprising conductive lines, wherein the lines have air as a dielectric between them, are encapsulated by an adhesion-promotion barrier layer, or both.

Claims

1. A process for manufacturing a microprocessor, the process comprising:

(a) creating a plurality of adjacent structures having a solid fill between the adjacent structures;

(b) creating at least one layer above said adjacent structures and said fill;

(c) creating at least one discrete pathway to said fill through said layer; and

(d) converting said fill to a gas that escapes through said pathway, leaving an air void between said adjacent structures.

2. The process according to claim 1, wherein said fill comprises amorphous carbon.

3. The process according to claim 2, wherein step (d) comprises heating the amorphous carbon fill in the presence of oxygen at a temperature greater than about 100°

C.

4. The process according to claim 3, wherein step (d) comprises said heating at a temperature of about 400°

C.

5. The process according to claim 1 wherein step (a) includes creating a plurality of conductive lines.

6. The process according to claim 5 wherein step (a) includes creating a plurality of conductive lines completely surrounded by an adhesion-promotion barrier layer.

7. A process for manufacturing a microprocessor, the process comprising:

(a) creating a plurality of adjacent structures having a solid fill with a top surface between the adjacent structures, by;

(i) creating a plurality of conductive lines, each having a top surface and at least one first adhesion-promotion barrier layer underneath each line and between each line and the fill adjacent to each line;

(ii) expanding said fill to raise the fill top surface higher than the conductive line top surface;

(iii) applying at least one second adhesion-promotion barrier layer over said fill top surface and said conductive line top surface; and

(iv) removing said at least one second adhesion-promotion barrier layer except over said conductive line top surface, leaving each conductive line encapsulated by said first and second adhesion-promotion barrier layers;

(b) creating at least one layer above said adjacent structures and said fill;

(c) creating at least one pathway to said fill through said layer; and

(d) converting said fill to a gas that escapes through said pathway, leaving an air void between said adjacent structures.

8. A process for manufacturing a microprocessor on a substrate, the process comprising:

(a) applying a first layer of amorphous carbon over the substrate;

(b) creating a plurality of trenches in said first layer of amorphous carbon;

(c) applying a first conductive layer over said first layer of amorphous carbon and in said trenches;

(d) removing said first conductive layer except in said trenches, leaving a plurality of conductive lines, one in each trench, having amorphous carbon between said conductive lines;

(e) applying a first cap layer,

(f) creating one or more cutouts in said first cap layer, each cutout creating an opening that exposes a portion of one of said conductive lines and a portion of said first layer of amorphous carbon adjacent to the conductive lines;

(g) applying a second layer of amorphous carbon over said first cap layer, filling said cutouts;

(h) removing said second layer of amorphous carbon except in said cutouts, leaving patches of amorphous carbon in said cutouts;

(i) applying a second cap layer over said first cap layer and over said patches;

(j) creating one or more discrete vias in said second cap layer, one over each patch, each via penetrating to the patch in the portion of the patch over the conductive line; and

(k) heating said substrate in the presence of oxygen to oxidize the amorphous carbon to a carbonaceous gas that escapes through each of said vias, leaving air voids between adjacent conductive lines.

9. The process according to claim 8, wherein step (k) comprises heating the substrate at a temperature greater than about 100°

C.

10. The process according to claim 9, wherein step (k) comprises heating the substrate at a temperature of about 400°

C.

11. The process according to claim 8 further comprising the step of:

(l) applying a second conductive layer over said second cap layer and in said vias; and

(m) removing said second conductive layer except in said vias.

12. A process for manufacturing a microprocessor on a substrate, the process comprising the steps of:

(a) creating a plurality of conductive lines having fill between the conductive lines, each conductive line having a top surface and at least one lower adhesion-promotion barrier layer underneath each line and between each line and the fill adjacent to each line, the fill having a top surface;

(b) expanding said fill to raise the fill top surface higher than the conductive line top surface;

(c) applying at least one upper adhesion-promotion barrier layer over said fill top surface and over said conductive line top surface; and

(d) removing said at least one upper adhesion-promotion barrier layer except over said conductive line top surface, leaving each conductive line encapsulated by said upper and lower adhesion-promotion barrier layers.

13. The process according to claim 12, wherein said fill comprises amorphous carbon and step (a) includes the steps of:

(i) applying over the substrate a layer of amorphous carbon;

(ii) creating one or more trenches in said amorphous carbon;

(iii) applying at least one lower adhesion-promotion barrier layer over said amorphous carbon including in said trenches;

(iv) applying a conductive layer over said at least one lower adhesion-promotion barrier layer and in said trenches; and

(v) removing said conductive layer and said at least one lower adhesion-promotion barrier layer except in said trenches;

and wherein expanding said fill in step (b) comprises heating said amorphous carbon in an inert atmosphere absent oxygen.

14. The process according to claim 13, wherein heating said amorphous carbon in an inert atmosphere absent oxygen in step (b) comprises heating said amorphous carbon at a temperature greater than about 300°

C for at least about 3½

hours.

15. The process according to claim 14, wherein heating said amorphous carbon in an inert atmosphere absent oxygen in step (b) comprises heating said amorphous carbon at a temperature between about 325°

C and 425°

C.

16. The process according to claim 15, wherein heating said amorphous carbon in an inert atmosphere absent oxygen in step (b) comprises heating said amorphous carbon at a temperature of about 410°

C.

17. The process according to claim 13 wherein in step (a)(iii) applying said at least one lower adhesion-promotion barrier layer comprises applying a single layer that is both an adhesion-promotion and a barrier layer, and in step (c) applying said at least one upper adhesion-promotion barrier layer comprises applying a single layer that is both an adhesion-promotion and a barrier layer.

18. The process according to claim 13 wherein in step (a)(iii) applying said at least one lower adhesion-promotion barrier layer comprises applying a first lower layer that is a barrier layer and then applying a second lower layer that is an adhesion-promotion layer, and in step (c) applying said at least one upper adhesion-promotion barrier layer comprises applying a first upper layer that is an adhesion-promotion layer and then applying a second upper layer that is a barrier layer.

19. The process according to claim 12 further comprising the steps of:

(e) evacuating the fill, leaving gaps between said conductive lines; and

(f) filling said gaps with a dielectric material.

20. The process according to claim 13 further comprising the steps of:

(e) heating the amorphous carbon in the presence of oxygen to form a carbonaceous gas that dissipates, leaving gaps between said conductive lines; and

(f) filling said gaps with a dielectric material.

21. The process according to claim 12 further comprising the steps of:

(e) creating at least one layer above said lines and said fill;

(f) creating at least one pathway to said fill through said layer; and

(g) converting said fill to a gas that escapes through said pathway, leaving an air void between adjacent lines.

22. The process according to claim 13 further comprising the steps of:

(e) applying a cap layer;

(f) creating at least one cutout in said cap layer, each cutout creating an opening that exposes a portion of one of said conductive lines and a portion of the amorphous carbon adjacent to said conductive lines;

(g) applying a second layer of amorphous carbon over said cap layer, filling said cutouts;

(h) removing said second layer of amorphous carbon except in said cutouts, leaving patches of amorphous carbon;

(i) applying a second cap layer over said first cap layer and over said patches;

(j) creating at least one via in said second cap layer, each via penetrating to a patch in a portion that is over one of said conductive lines; and

(k) heating said substrate in the presence of oxygen to oxidize the amorphous carbon to a carbonaceous gas that escapes through each of said vias, leaving air voids between adjacent conductive lines.

23. The process according to claim 22 further comprising the steps of:

(l) applying a second conductive layer over said second cap layer and in said at least one via; and

(m) removing said second conductive layer except in said at least one via.