Wafer level package

• US 6,268,642 B1
• Filed: 04/26/1999
• Issued: 07/31/2001
• Est. Priority Date: 04/26/1999
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Lin, Cheng-Te, Hsuan, Min-Chih
• Primary Examiner(s): Tran, Minh Loan
• Assistant Examiner(s): THAI, LUAN C
• Application Number:
  US09/299,706
• Time in Patent Office: 827 Days
• Field of Search: 257/620, 257/686, 257/780, 257/779, 257/621, 257/622, 257/623, 257/624, 257/626, 257/738, 257/772, 257/773, 438/113, 438/114, 438/110
• US Class Current: 257/620
• CPC Class Codes: H01L 2224/05022 the internal layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05556 in side view
• CPC Class Codes: H01L 2224/05558 conformal layer on a patterned surface
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/13016 in side view
• CPC Class Codes: H01L 2224/13027 the bump connector being offset with respect to the bonding area, e.g. bond pad
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16105 the bump connector connecting bonding areas being not aligned with respect to each other
• CPC Class Codes: H01L 2224/16106 the bump connector connecting one bonding area to at least two respective bonding areas
• CPC Class Codes: H01L 2224/16157 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 2224/85447 Copper (Cu) as principal constituent
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/00015 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed as prior art
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3011 : Impedance

Abstract

A wafer level package structure. The method of forming the wafer level package structure includes covering a silicon chip having a plurality of integrated circuit devices thereon with an insulation layer. Next, a plurality of bonding pads is formed on the periphery of the silicon chip above the insulation layer. The bonding pads are formed such that each bonding pad is electrically connected to the terminal of an integrated circuit device. Thereafter, a passivation layer is deposited over the insulation layer and the bonding pads, and then openings that expose a portion of the bonding pad are formed. Subsequently, a metallic layer is formed on the sidewalls and the exposed bonding pad area. The metallic layer also extends over the passivation layer in the neighborhood of the opening and towards the edge of the wafer chip. Next, a layer of packaging material is deposited over the passivation layer. Finally, a metallic bump is formed over the exposed metallic layer lying above each opening.

Claims

1. A wafer level package, comprising:

a silicon chip having at least one integrated circuit device;

an insulation layer covering the integrated circuit device;

a plurality of bonding pads above the insulation layer and distributed along the edges of the silicon chip, wherein each bonding pad is electrically connected to a terminal of the integrated circuit device;

a passivation layer covering the insulation layer and a portion of the bonding pad, wherein the passivation layer has a plurality of openings each exposing a portion of the bonding pad;

a metallic layer covering the interior side walls of the opening, the exposed bonding pad and the passivation layer surrounding the opening, and a portion of the metallic layer even extends from the opening to the edge of the silicon chip;

a packaging layer over the passivation layer outside the area with metallic layer; and

a plurality of metallic bumps over the metallic layer above each opening wherein the metallic bumps are located next to the edge of the silicon chip so that both a top surface and an outer surface of the metallic bump can act as a contacting area for external connections.

2. The wafer level package of claim 1, wherein the integrated circuit device comprises a MOS transistor, a resistor, a capacitor, an inductor, or a bipolar transistor or a combination thereof.

3. The wafer level package of claim 1, wherein the bonding pad is connected to a terminal of the integrated circuit device via a metallic interconnect passing through the insulation layer.

4. The wafer level package of claim 1, wherein the passivation layer comprises silicon oxide, silicon nitride, polyimide or a combination thereof.

5. The wafer level package of claim 1, wherein the metallic layer comprises copper, nickel, silver, palladium, palladium-nickel alloy, gold, titanium, or titanium nitride or a combination thereof.

6. The wafer level package of claim 1, wherein the packaging layer comprises epoxy.

7. The wafer level package of claim 1, wherein the metallic bump comprises lead-tin alloy.

8. A silicon wafer structure for producing wafer level package, comprising:

a silicon wafer made up of a plurality of silicon chips with each chip having at least an integrated circuit device, and furthermore two neighboring silicon chips are connected by a scribe line section;

an insulation layer covering the silicon wafer;

a plurality of bonding pads distributed around the edges of each silicon chip, and each bonding pad is electrically connected to a terminal of the integrated circuit device;

a plurality of circuits for chip testing formed on the scribe line sections, and the circuits are electrically connected to the integrated circuit device and bonding pad of a neighboring silicon chip;

a plurality of contacting points leading to the circuit on each scribe line section;

a passivation layer formed over the insulation layer and a portion of each bonding pad such that a plurality of openings that expose the respective bonding pads is formed;

a metallic layer covering the interior side walls of the opening, the exposed bonding pad and the passivation layer surrounding the opening, and a portion of the metallic layer even extends from the opening to the edge of the silicon chip;

a packaging layer over the passivation layer outside the area with metallic layer; and

a plurality of metallic bumps over the metallic layer above each opening wherein the metallic bumps are located next to the edge of the silicon chip so that both a top surface and an outer surface of the metallic bump can act as a contacting area for external connections.

9. The silicon wafer of claim 8, wherein the integrated circuit device comprises a MOS transistor, a resistor, a capacitor, an inductor, or a bipolar transistor or a combination thereof.

10. The silicon wafer of claim 8, wherein the bonding pad is connected to a terminal of the integrated circuit device via a metallic interconnect passing through the insulation layer.

11. The silicon wafer of claim 8, wherein the passivation layer comprises silicon oxide, silicon nitride, or polyimide or a combination thereof.

12. The silicon wafer of claim 8, wherein the metallic layer comprises copper, nickel, silver, palladium, palladium-nickel alloy, gold, titanium or titanium nitride or a combination thereof.

13. The silicon wafer of claim 8, wherein the packaging layer comprises epoxy.

14. The silicon wafer of claim 8, wherein the metallic bump comprises lead-tin alloy.

15. A stack-up structure of wafer level packages, comprising:

a wafer level packages carrier having at least a bottom panel and a plurality of vertical side panels attached to the edges of the bottom panel, wherein the bottom panel has a plurality of first contacting points on the upper side of the bottom panel and a plurality of second contacting points on the lower side of the bottom panel such that each first contacting point is electrically coupled to a second contacting point, furthermore, the vertical side panel also has a plurality of conductive lines along its surface with each line electrically coupled to one of the first contacting points; and

a plurality of wafer level packages, each of these wafer level packages comprising;

a silicon chip having at least one integrated circuit device;

an insulation layer covering the integrated circuit device;

a plurality of bonding pads above the insulation layer and distributed along the edges of the silicon chip, wherein each bonding pad is electrically connected to a terminal of the integrated circuit device;

a passivation layer covering the insulation layer and a portion of the bonding pad, wherein the passivation layer has a plurality of openings each exposing a portion of the bonding pad;

a metallic layer covering the interior side walls of the opening, the exposed bonding pad and the passivation layer surrounding the opening, and a portion of the metallic layer even extends from the opening to the edge of the silicon chip;

a packaging layer over the passivation layer outside the area with metallic layer; and

a plurality of metallic bumps over the metallic layer above each opening, wherein

the wafer level packages stack up from the bottom panel such that the metallic bumps of the package closest to the bottom panel is able to contact the first contacting points of the carrier whereas the metallic bumps of other packages contact the conductive lines along the vertical side panels of the carrier.

16. The stack-up structure of claim 15, wherein the integrated circuit device is selected from the group consisting of a MOS transistor, a resistor, a capacitor, an inductor, a bipolar transistor and the combination thereof.

17. The stack-up structure of claim 15, wherein the bonding pad is connected to one terminal of the integrated circuit device via a metallic interconnect passing through the insulation layer.

18. The stack-up structure of claim 15, wherein the passivation layer is selected from the group consisting of a silicon oxide layer, a silicon nitride layer, a polyimide layer and the combination thereof.

19. The stack-up structure of claim 15, wherein the metallic layer is selected from the group consisting of a copper layer, a nickel layer, a silver layer, a palladium layer, a palladium-nickel alloy layer, a gold layer, a titanium layer, a titanium nitride layer and the combination thereof.

20. The stack-up structure of claim 15, wherein the packaging layer can be an epoxy layer.

21. The stack-up structure of claim 15, wherein the metallic bump can be made from a material including a lead-tin alloy.