Non-volatile storage latch

• US 6,269,027 B1
• Filed: 04/14/1998
• Issued: 07/31/2001
• Est. Priority Date: 04/14/1998
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Honeywell Incorporated (Honeywell International Inc.)
• Inventors: Hurst, Allan T. Jr., Sather, Jeff S., Gadbois, Jason B.
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): AUDUONG, GENE NGHIA
• Application Number:
  US09/059,871
• Time in Patent Office: 1,204 Days
• Field of Search: 365/158, 365/171, 365/66, 365/55, 365/74, 365/225.5, 365/46, 365/48, 365/50, 365/62, 365/130, 365/131, 365/154, 365/189.05, 365/97, 365/185.08
• US Class Current: 365/189.05
• CPC Class Codes: G11C 11/161 details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods
• CPC Class Codes: G11C 14/0081 and the nonvolatile element is a magnetic RAM [MRAM] element or ferromagnetic cell
• CPC Class Codes: G11C 7/20 Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
• CPC Class Codes: H03K 3/356008 ensuring a predetermined initial state when the supply voltage has been applied; storing the actual state when the supply voltage fails digital storage cells each combining volatile and non-volatile storage properties G11C14/00
• CPC Class Codes: H03K 3/45 by the use, as active elements, of non-linear magnetic or dielectric devices
• CPC Class Codes: H10B 61/22 of the field-effect transistor [FET] type

Abstract

In one aspect of the present invention, a non-volatile latching element is provided that includes one or more magnetic elements therein. By programming the magnetic elements to appropriate resistance values, the latching element assumes a pre-programmed state upon power up. The magnetic elements are preferably programmed using either a one or two layer word line. In another aspect of the present invention, the magnetic elements are formed as pseudo-spin valve structures utilizing only CoFe as the active ferromagnetic layers, with one ferromagnetic layer thinner than the other. This simplifies the design while maintaining the high moment material to achieve large GMR ratios.

Claims

1. A non-volatile latch, comprising:

a latching element powered by a power supply, said latching element selectively storing a bit of data having one of two stable states; and

first magnetic means interposed between a first portion of said latching element and said power supply for providing a first magnetically programmable resistance therein, said first magnetic means causing said latching element to assume a desired one of the two stable states upon power-up of said power supply.

2. A non-volatile latch according to claim 1 further comprising:

second magnetic means interposed between a second portion of said latching element and said power supply for providing a second magnetically programmable resistance therein.

3. A non-volatile latch according to claim 1 wherein said latching element comprises a first inverting logic element and a second inverting logic element coupled together in a cross-coupled configuration, wherein each of said first and second inverting logic elements has a first power supply terminal and a second power supply terminal.

4. A non-volatile latch according to claim 3 wherein said first magnetic means is connected between the first power supply terminal of said first inverting logic element and a first voltage;

said second power supply terminal of said first inverting logic element being coupled to a second voltage.

5. A non-volatile latch according to claim 4 further comprising:

a second magnetic means for providing a second magnetically programmable resistance value, wherein said second magnetic means is connected between the first power supply terminal of said second inverting logic element and the first voltage;

said second power supply terminal of said second inverting logic elements coupled to the second voltage.

6. A non-volatile latch according to claim 5 wherein the first voltage is positive with respect to ground, and the second voltage is ground.

7. A non-volatile latch according to claim 5 wherein the first voltage is ground, and the second voltage is positive with respect to ground.

8. A non-volatile latch according to claim 4 further comprising a second magnetic means for providing a second magnetically programmable resistance value, wherein said second magnetic means is connected between the second power supply terminal of said second inverting logic element and the second voltage;

said first power supply terminal of said second inverting logic element coupled to the first voltage.

9. A non-volatile latch according to claim 1 wherein said first magnetic means comprises an AMR material.

10. A non-volatile latch according to claim 1 wherein said first magnetic means comprises a GMR material.

11. A non-volatile latch according to claim 1 wherein said first magnetic means comprises a CMR material.

12. A non-volatile latch according to claim 1 wherein said first magnetic means comprises a spin tunneling element.

13. A non-volatile latch according to claim 1 wherein said first magnetic means comprises a pseudo spin valve element.

14. A non-volatile latch powered by a first voltage and a second voltage, comprising:

a first p-channel transistor having a gate terminal, a source terminal and a drain terminal, said source terminal of said first p-channel transistor connected to the first voltage;

a first n-channel transistor having a gate terminal, a source terminal and a drain terminal, said drain terminal of said first n-channel transistor connected to said drain terminal of said first p-channel transistor, and said gate terminal of said first n-channel transistor connected to said gate terminal of said first p-channel transistor;

a second p-channel transistor having a gate terminal, a source terminal and a drain terminal, said source terminal of said second p-channel transistor connected to the first voltage;

a second n-channel transistor having a gate terminal, a source terminal and a drain terminal, said drain terminal of said second n-channel transistor connected to said drain terminal of said second p-channel transistor, and said gate terminal of said second n-channel transistor connected to said gate terminal of said second p-channel transistor;

said drain terminal of said first n-channel transistor connected to said gate terminal of said second n-channel transistor, and said drain terminal of said second n-channel transistor connected to said gate terminal of said first n-channel transistor, and

a first magnetic means for providing a first magnetically programmable resistance value connected between the source of the first n-channel transistor and the second voltage.

15. A non-volatile latch according to claim 14 wherein said first magnetic means comprises a material selected from the group consisting of an AMR material, a GMR material and a CMR material.

16. A non-volatile latch according to claim 14 wherein said first magnetic means comprises a spin tunneling element.

17. A non-volatile latch according to claim 14 wherein said first magnetic means comprises a spin valve element.

18. A non-volatile latch according to claim 14 further comprising:

a second magnetic means for providing a second magnetically programmable resistance value connected between the source of the second n-channel transistor and the second voltage.

19. A non-volatile latch according to claim 14 wherein the first voltage is positive with respect to ground, and the second voltage is ground.

20. A non-volatile latch according to claim 14 further includes a programming means for programming the resistance value of said first magnetic means.

21. A non-volatile latch according to claim 20 wherein the programmable resistance value of said first magnetic means has two stable states, and said programming means programs the resistance value of said first magnetic means to be in one of the two stable states.

22. A non-volatile latch according to claim 21 wherein said programming means includes a writing means that is spaced from said first magnetic means for writing one of the two stable states into said first magnetic means.

23. A non-volatile latch according to claim 22 wherein the programmable resistance value of said second magnetic means has two stable states, and said programming means programs the resistance value of said second magnetic means to be in one of the two stable states.

24. A non-volatile latch according to claim 23 wherein said programming means programs the resistance value of said second magnetic means in the opposite state as the first magnetic means.