Semiconductor memory having a redundancy judgment circuit

• US 6,269,034 B1
• Filed: 06/14/2000
• Issued: 07/31/2001
• Est. Priority Date: 06/14/1999
• Status: Expired due to Term

• Current Assignee: Longitude Licensing Limited (Vector Capital Corporation)
• Original Assignee: NEC Corporation
• Inventors: Shibuya, Masahiro
• Primary Examiner(s): Ho, Hoai V.
• Application Number:
  US09/593,210
• Time in Patent Office: 412 Days
• Field of Search: 365/200, 365/194, 365/233, 365/189.01, 365/230.01
• US Class Current: 365/194
• CPC Class Codes: G11C 29/842 by introducing a delay in a signal path
• CPC Class Codes: G11C 29/844 by splitting the decoders in stages

Abstract

In a semiconductor memory having a redundancy circuit, when a defective cell is replaced with a redundancy cell, activation of a normal word line is retarded until it is judged whichever of a redundancy word line and a normal word line should be activated. The semiconductor memory has address pre-decoders enabling selection and driving of a normal word line, and a redundancy control circuit for judging whether a redundancy word line should be activated. The address pre-decoders and redundancy control circuit are controlled mutually independently. Irrespective of whether a redundancy word line is used, a normal word line can be controlled earlier. Consequently, the action of the whole semiconductor memory can be speeded up.

Claims

1. A semiconductor memory device, comprising:

a plurality of normal memory cells;

a plurality of redundancy memory cells;

a plurality of normal word lines connected to said normal memory cells;

a plurality of redundancy word lines connected to said redundancy memory cells and including at least a first redundancy word line;

a normal word decoder for selecting and driving one of said normal word lines corresponding to an external address signal provided in response to a first clock signal;

a redundancy word decoder for driving said first redundancy word lines;

address judging means for judging whether said external address signal corresponds to the address of a defective normal memory cell; and

a redundancy control circuit having inputs connected to said address judging means and having outputs connected to said normal word decoder and said redundancy word decoder,

wherein said redundancy control circuit activates said redundancy word decoder and inactivates said normal word decoder in response to a second clock signal which is different from said first clock signal, if said external address signal corresponds to the address of a defective normal memory cell.

2. The semiconductor memory device according to claim 1, wherein said first clock signal is activated earlier than the activation of said second clock signal.

3. The semiconductor memory device according to claim 1, wherein said second clock signal is produced by delaying said first clock signal by a predetermined time.

4. The semiconductor memory device according to claim 1, wherein said redundancy control circuit keeps said normal word decoder active until said redundancy word decoder is activated according to the result of said address judging means.

5. The semiconductor memory device of claim 1, further comprising a plurality of address pre-decoders for receiving a row address signal and said first clock signal,

wherein said address pre-decoders and said redundancy control circuit are controlled mutually independently.

6. The semiconductor memory device of claim 5, wherein said first clock signal is driven high earlier regardless of a level to which a redundancy judgment signal from said address judging means is driven.

7. The semiconductor memory device of claim 1, wherein a normal word line is controlled prior to a redundancy word line and regardless of whether said redundancy word line is used, and

wherein a judgement of whether said normal word line or said redundancy word line is used is dependent on other than a predetermined signal.

8. A semiconductor memory device, comprising:

a plurality of normal word lines connected to normal memory cells;

a plurality of redundancy word lines connected to redundancy memory cells;

a row address buffer supplied with external address signals;

an address judging circuit connected to said row address buffer;

a plurality of address pre-decoders connected to said row address buffer, and provided with a row address signal in response to a first clock signal;

a redundancy control circuit connected to said address judging circuit, and provided with output signals of said address judging circuit in response to a second clock signal;

a redundancy word decoder connected to said redundancy control circuit, and driving one of said redundancy word lines in response to a redundancy word line enabling signal generated from said redundancy control circuit; and

a normal word decoder connected to said address pre-decoders, and driving one of said normal word lines in response to a normal word line enabling signal generated from said redundancy control circuit,

wherein said first clock signal is activated earlier than said second clock signal, when said row address signals corresponds to a defective memory cell in said normal memory cell, said redundancy control circuit sets said redundancy word decoder activating and said normal word decoder inactivating.

9. The semiconductor memory device according to claim 8, wherein said address pre-decoders are activated before said redundancy control circuit sets said redundancy word decoder and said normal word decoder.

10. The semiconductor memory device according to claim 8, wherein said second clock signal is activated for a predetermined time delay from said first clock signal activating, said predetermined time delay is from a time of said address pre-decoders being activated to a time of an address pre-decoded signal being carried to said normal word decoder.

11. The semiconductor memory device according to claim 8, wherein said redundancy control circuit comprises a plurality of NOR circuits which generate said redundancy word line enable signal in response to said second clock signal, an AND circuit which is provided with output signals of said NOR circuits and generates said normal word line enable signal.

12. The semiconductor memory device of claim 8, wherein said address pre-decoders and said redundancy control circuit are controlled mutually independently.

13. The semiconductor memory device of claim 12, wherein said first clock signal is driven high earlier regardless of a level to which said outputs signals of said address judging circuit are driven.

14. The semiconductor memory device of claim 8, wherein normal word line is controlled prior to a redundancy word line and regardless of weather said redundancy word line is used, and

wherein a judgement of weather said normal word line or said redundancy word line is used is dependent on other than predetermined signal.

15. A semiconductor memory device, comprising:

a plurality of normal word lines connected to normal memory cells;

a plurality of redundancy word lines connected to redundancy memory cells;

a plurality of row address buffers supplied with each of external address signals;

an address judging circuit connected to said row address buffers;

a plurality of address pre-decoders connected to each of said row address buffers, and provided with each of row address signals in response to a first clock signal;

a redundancy control circuit connected to said address judging circuit, and provided with output signals of said address judging circuit in response to a second clock signal;

a redundancy word decoder connected to said redundancy control circuit, and driving one of said redundancy word lines in response to a redundancy word line enabling signal generated from said redundancy control circuit;

a cell plate selection circuit, connected to said address pre-decoders and said redundancy control circuit, supplied with a sense amplifier enabling signal and generating a sense amplifier driving signal; and

a normal word decoder connected to said address pre-decoders,

wherein said first clock signal is activated earlier than said second clock signal.

16. A semiconductor memory device, comprising:

an address judging circuit;

a plurality of address pre-decoders provided with each of row address signals in response to a first clock signal;

a redundancy control circuit connected to said address judging circuit, and provided with output signals of said address judging circuit in response to a second clock signal;

a redundancy word decoder connected to said redundancy control circuit, and driving a redundancy word line in response to a redundancy word line enabling signal generated from said redundancy control circuit; and

a cell plate selection circuit connected to said address pre-decoders and said redundancy control circuit, supplied with a sense amplifier enabling signal and generating a sense amplifier driving signal.

17. The semiconductor memory device of claim 16, further comprising:

a normal word decoder connected to said address pre-decoders.

18. The semiconductor memory device of claim 16, further comprising:

a plurality of normal word lines connected to normal memory cells;

a plurality of redundancy word lines connected to redundancy memory cells; and

a plurality of row address buffers supplied with each of external address signals, said address judging circuit being connected to said row address buffers.

19. The semiconductor memory device of claim 16, wherein said first clock signal is activated earlier than said second clock signal.

20. The semiconductor memory device of claim 16, wherein the redundancy word decoder and the normal word decoder are controlled by the redundancy control circuit in response to said second clock signal.

21. The semiconductor memory device of claim 16, wherein a normal word line is controlled prior to a redundancy word line and regardless of whether said redundancy word line is used, and wherein a judgement of whether said normal word line or said redundancy word line is used is dependent on other than a predetermined signal.