Wide capture range circuitry

• US 6,269,058 B1
• Filed: 01/04/1999
• Issued: 07/31/2001
• Est. Priority Date: 01/04/1999
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Fujinara, Futoshi, Yamanoi, Koyu, Kobayashi, Hiroshi
• Primary Examiner(s): EDUN, MUHAMMAD N
• Application Number:
  US09/225,125
• Time in Patent Office: 939 Days
• Field of Search: 369/47.1, 369/47.11, 369/47.15, 369/47.28, 369/47.29, 369/47.3, 369/47.36, 369/47.48, 369/53.1, 369/53.34, 369/59.1, 369/59.12, 369/60.01, 360/33.1, 360/36.1, 360/37.1, 360/39, 360/42, 360/51, 360/69, 360/73.01
• US Class Current: 369/47.28
• CPC Class Codes: G11B 19/28 Speed controlling, regulating, or indicating G11B19/24 takes precedence
• CPC Class Codes: G11B 2220/213 Read-only discs
• CPC Class Codes: G11B 2220/2545 CDs
• CPC Class Codes: G11B 2220/2562 DVDs [digital versatile discs]; Digital video discs; MMCDs; HDCDs
• CPC Class Codes: G11B 27/3027 used signal is digitally coded
• CPC Class Codes: H03L 7/113 using frequency discriminator

Abstract

Circuitry and method for synchronizing operating speeds of signal processing devices to the data rate of a signal. It applies in particular to Compact Disk (CD) and Digital Versatile Disk (DVD) drives to be used with portable devices. The circuitry does not require clock synchronization speeds in excess of the instantaneous data rate used by the disk drive and also reduces power consumption.

Claims

1. A system employing a drive having a speed synchronization capacity, the synchronization capacity comprising:

first and second signal sources generating a first and a second signal, respectively;

a first circuit, for receiving said first and second signals in order to establish a first estimated synchronization frequency near that of an operating speed of the drive and for generating a third signal containing said first estimated frequency;

a second circuit, for receiving said third signal in order to refine said first estimated frequency and for generating a fourth signal containing said refined estimated frequency;

a third circuit, for receiving said fourth signal in order to establish a desired frequency of operation with a predetermined variance, and to generate a fifth signal containing said desired frequency; and

a fourth circuit, for receiving said fifth signal in order to detect and lock said desired frequency as a synchronization frequency.

2. The system of claim 1 wherein said signal sources are first and second voltage controlled oscillators (VCOs).

3. The system of claim 2 wherein said first VCO is a data synchronization VCO (DSVCO) and said second VCO is a time base generator VCO (TBGVCO).

4. The system of claim 1 wherein said fourth circuit comprises a Phase-Locked Loop (PLL).

5. The system of claim 1 wherein a current divider is used to attain said estimates.

6. The system of claim 1 wherein said first circuit comprises first and second gates, an inverter, first and second n-bit counters, a synchronization pattern detector, a first multiplexer, and first and second registers, functionally interconnected as said first circuit,

wherein said first circuit is functionally connected to an external logic device so as to determine a first synchronization frequency estimate.

7. The system of claim 6 wherein said n-bit counters are 6-bit current mode logic (CML) counters.

8. The system of claim 1 wherein said third circuit comprises a second multiplexer, an adjustable window circuit, an m-bit counter, a synchronization determination apparatus, a p-bit up/down counter, functionally interconnected as said third circuit, for determining a fine adjustment synchronization frequency,

wherein, said third circuit receives inputs from said first and second current sources, an adjustable external input element, and said second circuit.

9. The system of claim 8 wherein said m-bit counters are 16-bit counters and said p-bit counters are 5-bit counters.

10. A method for synchronizing the operating speed of a system, comprising:

providing reference and timing signals;

detecting and capturing first, second and third estimates of a frequency near that of an operating speed of the drive, said third estimate having a desired center value and variance;

identifying a desired synchronization pattern within said third estimate and generating a synchronization indication; and

phase locking said synchronization indication.

11. The method of claim 10, wherein said reference and timing signals are provided by a TBGVCO and a DSVCO.

12. The method of claim 11, further comprising generating a proportional frequency by dividing a current from said TBGVCO to said DSVCO.

13. The method of claim 11, further comprising calculating said DSVCO'"'"'s center frequency from the relationship:

14. The method of claim 11, further comprising:

a) restarting said DSVCO by entering a “

zero phase”

restart mode;

b) setting signal Outof5 if one of the following occurs;

i) encountering five DL50 signals;

ii) missing said synchronization pattern; and

c) powering off said synchronization circuit if a powerdb bit is set.

15. The method of claim 10, wherein said phase locking is accomplished using a PLL.

16. The method of claim 10, wherein said estimates are derived by using a current divider to alter current.

17. The method of claim 10, further comprising using a Phase-Locked Loop (PLL) to accomplish phase detection and locking.

18. The method of claim 10, wherein frequency is shifted by forwarding an up/down count signal, together with said reference signal, to an up/down counter for implementing a frequency shift.

19. A disk drive having a speed synchronization capacity, the synchronization capacity comprising:

first and second signal sources generating a first and a second signal, respectively;

a first circuit, for receiving said first and second signals in order to establish a first estimated synchronization frequency near that of an operating speed of the drive and for generating a third signal containing said first estimated frequency;

a second circuit, for receiving said third signal in order to refine said first estimated frequency and for generating a fourth signal containing said refined estimated frequency;

a third circuit, for receiving said fourth signal in order to establish a desired frequency of operation with a predetermined variance, and to generate a fifth signal containing said desired frequency; and

a fourth circuit, for receiving said fifth signal in order to detect and lock said desired frequency as a synchronization frequency.

20. The drive of claim 19 wherein said signal sources are first and second voltage controlled oscillators (VCOs).

21. The drive of claim 20 wherein said first VCO is a data synchronization VCO (DSVCO) and said second VCO is a time base generator VCO (TBGVCO).

22. The drive of claim 19 wherein said fourth circuit comprises a Phase-Locked Loop (PLL).

23. The drive of claim 19 wherein a current divider is used to attain said estimates.

24. A method for synchronizing the operating speed of a disk drive, comprising:

providing reference and timing signals;

detecting and capturing first, second and third estimates of a frequency near that of an operating speed of the drive, said third estimate having a desired center value and variance;

identifying a desired synchronization pattern within said third estimate and generating a synchronization indication; and

phase locking said synchronization indication.

25. The method of claim 24, wherein said reference and timing signals are provided by a TBGVCO and a DSVCO.

26. The method of claim 25, further comprising generating a proportional frequency by dividing a current from said TBGVCO to said DSVCO.

27. The method of claim 25, further comprising calculating said DSVCO'"'"'s center frequency from the relationship:

28. The method of claim 25, further comprising:

restarting said DSVCO by entering a “

zero phase”

restart mode;

setting signal Outof5 if one of the following occurs;

encountering five DL50 signals;

missing said synchronization pattern; and

powering off said synchronization generation capability if a powerdb bit is set.

29. The method of claim 24, wherein said phase locking is accomplished using a PLL.

30. The method of claim 24, wherein said estimates are derived by using a current divider to alter current.

31. The method of claim 24, further comprising using a Phase-Locked Loop (PLL) to accomplish phase detection and locking.

32. The method of claim 24, wherein frequency is shifted by forwarding an up/down count signal, together with said reference signal, to an up/down counter for implementing a frequency shift.