Serial line synchronization method and apparatus
First Claim
1. An apparatus for decoding a serial transmission having a data signal, a clock signal and a frame synchronization signal encoded as a biphase mark signal being defined by a modulation protocol and having a protocol violation representing said frame synchronization signal, comprsing:
- means for detecting transitions in said bi-phase mark signal;
means for deriving a toggle clock signal from said bi-phase mark signal;
means for generating, in response to the detected transitions and said toggle clock signal, a bit clock signal;
means for recovering, in response to the detected transitions and said bit clock signal, said data signal; and
means for recovering, in response to the detected transitions and said bit clock signal, said frame synchronization signal.
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Accused Products
Abstract
Apparatus, and an accompanying method, for transmitting a frame synchronization signal and a data signal simultaneously through a serial transmission medium (170). Specifically within a data transmitter (105), a frame synchronization signal, a clock signal and a data signal, are encoded to form a single bi-phase mark signal that is defined by a specific modulation protocol and the frame synchronization signal is incorporated into the bi-phase mark signal as a protocal violation. The bi-phase mark signal is then transmitted through a suitable serial transmission medium. A receiver (175), connected to the transmission medium, receives and amplifies an incoming bi-phase mark signal appearing on the medium, and, in turn, synthesizes the clock, frame synchronization, and data signals from this bi-phase mark signal.
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Citations
13 Claims
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1. An apparatus for decoding a serial transmission having a data signal, a clock signal and a frame synchronization signal encoded as a biphase mark signal being defined by a modulation protocol and having a protocol violation representing said frame synchronization signal, comprsing:
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means for detecting transitions in said bi-phase mark signal;
means for deriving a toggle clock signal from said bi-phase mark signal;
means for generating, in response to the detected transitions and said toggle clock signal, a bit clock signal;
means for recovering, in response to the detected transitions and said bit clock signal, said data signal; and
means for recovering, in response to the detected transitions and said bit clock signal, said frame synchronization signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. An apparatus for synchronizing the transmission of a data signal, that is organized Into sequential frames each containing a sequence of data bits, in a data transmission system, comprising:
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an encoder that, prior to transmission, encodes the data signal and a clock signal and a frame synchronization signal of the transmission system into a single bit stream formatted as a bi-phase mark signal, the encoder comprising means for encoding the frame synchronization signal as a protocol violation of said bi-phase mark signal; and
a decoder that, after transmission, decodes the bi-phase mark signal to recover the data, clock, and frame synchronization signals, comprising means for detecting transitions in said bi-phase mark signal;
means for deriving a toggle clock signal from said bi-phase mark signal;
means for generating, in response to the detected transitions and said bit clock signal, said data signal; and
means for recovering, in response to the deteted transitions and said bit clock signal, said frame synchronization signal. - View Dependent Claims (12, 13)
the protocol violation occurs during each sequence of bits that defines a frame of to data signal, and during a sequence of bit intervals fixed to a predetermined bit pattern; and
the predetermined bit pattern corresponds to a bit pattern of 1011 in the data signal.
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13. The apparatus of claim 11, wherein:
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the protocol violation occurs during each seguence of bits that defines a frame of the data signal, and during a sequence of bit intervals fixed to a predetermined bit pattern; and
the predetermined bit pattern triggers the decoder to recover the frame synchronization signal from the protocol violation.
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Specification