Serial line synchronization method and apparatus

• US 6,269,127 B1
• Filed: 03/19/1997
• Issued: 07/31/2001
• Est. Priority Date: 09/24/1992
• Status: Expired due to Term

• Current Assignee: Siemens Information And Communication Networks, Inc. (Siemens AG)
• Original Assignee: Siemens Information And Communication Networks, Inc. (Siemens AG)
• Inventors: Richards, Glenn L.
• Primary Examiner(s): TSE, YOUNG TOI
• Application Number:
  US08/820,919
• Time in Patent Office: 1,595 Days
• Field of Search: 375/219, 375/257, 375/282, 375/293, 375/333, 375/337, 375/360, 375/361, 375/362, 375/368, 341/70, 341/71, 341/72
• US Class Current: 375/282
• CPC Class Codes: H04J 3/0614 the synchronising signal being characterised by the amplitude, duration or polarity
• CPC Class Codes: H04L 25/4904 using self-synchronising codes, e.g. split-phase codes

Abstract

Apparatus, and an accompanying method, for transmitting a frame synchronization signal and a data signal simultaneously through a serial transmission medium (170). Specifically within a data transmitter (105), a frame synchronization signal, a clock signal and a data signal, are encoded to form a single bi-phase mark signal that is defined by a specific modulation protocol and the frame synchronization signal is incorporated into the bi-phase mark signal as a protocal violation. The bi-phase mark signal is then transmitted through a suitable serial transmission medium. A receiver (175), connected to the transmission medium, receives and amplifies an incoming bi-phase mark signal appearing on the medium, and, in turn, synthesizes the clock, frame synchronization, and data signals from this bi-phase mark signal.

Claims

1. An apparatus for decoding a serial transmission having a data signal, a clock signal and a frame synchronization signal encoded as a biphase mark signal being defined by a modulation protocol and having a protocol violation representing said frame synchronization signal, comprsing:

means for detecting transitions in said bi-phase mark signal;

means for deriving a toggle clock signal from said bi-phase mark signal;

means for generating, in response to the detected transitions and said toggle clock signal, a bit clock signal;

means for recovering, in response to the detected transitions and said bit clock signal, said data signal; and

means for recovering, in response to the detected transitions and said bit clock signal, said frame synchronization signal.

2. The apparatus of claim 1 wherein said bi-phase mark signal comprises a sequence of bit intervals and a zero bit in said data signal is encoded as a transition at the beginning of a respective bit interval and a one bit in said data signal is encoded as transitions at the beginning and the middle of a respective bit interval.

3. The apparatus of claim 2 wherein each of said bit intervals has a duration equivalent to a cycle of said clock signal.

4. The apparatus of claim 3 wherein said protocol violation in said bi-phase mark signal occurs simultaneously with a transition at the beginning of a bit interval, said protocol violation effectively removing the transition.

5. The apparatus of claim 4 further comprising means for producing, in response to the detected transitions, a mask signal for masking the detected transitions at a point where said protocol violation in said bi-phase mark signal has removed the transition.

6. The apparatus of claim 5 wherein the protocol violation occurs during a sequence of bit intervals fixed to a predetermined bit pattern, said bit pattern triggering the means for producing the mask signal and the means for recovering said frame synchronization signal from the protocol violation.

7. The apparatus of claim 1 further comprising means for filtering said bit clock signal to reproduce said clock signal.

8. The apparatus of claim 2 wherein the protocol violation occurs during a sequence of bit intervals fixed to a predetermined bit pattern.

9. The apparatus of claim 8, wherein the predetermined bit pattern corresponds to a bit pattern of 1011 in the data signal.

10. The apparatus of claim 8, wherein the predetermined bit pattern triggers the means for recovering said frame synchronization signal from the protocol violation.

11. An apparatus for synchronizing the transmission of a data signal, that is organized Into sequential frames each containing a sequence of data bits, in a data transmission system, comprising:

an encoder that, prior to transmission, encodes the data signal and a clock signal and a frame synchronization signal of the transmission system into a single bit stream formatted as a bi-phase mark signal, the encoder comprising means for encoding the frame synchronization signal as a protocol violation of said bi-phase mark signal; and

a decoder that, after transmission, decodes the bi-phase mark signal to recover the data, clock, and frame synchronization signals, comprising

means for detecting transitions in said bi-phase mark signal;

means for deriving a toggle clock signal from said bi-phase mark signal;

means for generating, in response to the detected transitions and said bit clock signal, said data signal; and

means for recovering, in response to the deteted transitions and said bit clock signal, said frame synchronization signal.

12. The apparatus of claim 11, wherein:

the protocol violation occurs during each sequence of bits that defines a frame of to data signal, and during a sequence of bit intervals fixed to a predetermined bit pattern; and

the predetermined bit pattern corresponds to a bit pattern of 1011 in the data signal.

13. The apparatus of claim 11, wherein:

the protocol violation occurs during each seguence of bits that defines a frame of the data signal, and during a sequence of bit intervals fixed to a predetermined bit pattern; and

the predetermined bit pattern triggers the decoder to recover the frame synchronization signal from the protocol violation.