Digital phase discriminations based on frequency sampling

• US 6,269,135 B1
• Filed: 01/14/1998
• Issued: 07/31/2001
• Est. Priority Date: 01/14/1998
• Status: Expired due to Term

• Current Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Tropian, Inc. (Panasonic Holdings Corporation)
• Inventors: Sander, Wendell
• Primary Examiner(s): Pham, Chi
• Assistant Examiner(s): Corrielus, Jean B.
• Application Number:
  US09/006,938
• Publication Number:
  US 20020063651A1 (withdrawn)
• Time in Patent Office: 1,294 Days
• Field of Search: 375/354, 375/377, 375/375, 375/355, 375/371, 327/144, 327/151, 327/3
• US Class Current: 375/354
• CPC Class Codes: G01R 25/00 Arrangements for measuring phase angle between a voltage and a current or between voltages or currents
• CPC Class Codes: H03D 13/006 and by sampling this signal by narrow pulses obtained from the second oscillation
• CPC Class Codes: H04L 7/0334 Processing of samples having at least three levels, e.g. soft decisions

Abstract

The present invention, generally speaking, provides a simple, all-digital method and apparatus for determining the phase of a first clock signal relative to a second clock signal. The first clock signal may be a digital approximation of a periodic analog signal such as an RF signal. A sampling technique is employed that produces a stream of digital bits containing relative phase information. From the stream of digital bits is formed a digital word indicative of the relative phase. The digital word may be formed using a digital filter. Advantageously, an extensive body of digital filtering techniques applicable to Sigma-Delta (sometimes referred to as Delta-Sigma) A/D converters may be applied directly to the digital stream. By using an appropriately-chosen weighting function, high accuracy may be obtained.

Claims

1. A method of determining the phase of a first clock signal using a second clock signal, comprising:

sampling the first clock signal in accordance with the second clock signal to produce a stream of digital bits or symbols wherein a frequency ratio of the first clock signal and the second clock signal is variable throughout a range including non-integer values; and

performing postprocessing of the stream of digital bits or symbols to form, from a substantial number of said digital bits or symbols, a digital word indicative of the phase;

wherein each digital bit or symbol of a sequence of consecutive digital bits or symbols represents a number of transitions n of a predetermined polarity of the first clock signal that occurred during a corresponding period in a sequence of consecutive periods of the second clock signal, where n is a non-negative integer.

2. The method of claim 1, wherein forming the digital word comprises filtering the stream of digital bits or symbols.

3. An apparatus for determent the phase of a first clock signal using a second clock signal, comprising:

means for sampling the first clock signal in accordance with the second clock signal to produce a stream of digital bits or symbols wherein a frequency ratio of the first and second clock signals is variable throughout a range including non-integer values; and

means for performing postprocessing of the stream of digital bits or symbols to form, from a substantial number of said digital bits or symbols, a digital word indicative of the phase;

wherein each digital bit or symbol of a sequence of consecutive digital bits or symbols represents a number of transitions n of a predetermined polarity of the first clock signal that occurred during a corresponding period in a sequence of consecutive periods of the second clock signal, where n is a non-negative integer.

4. The apparatus of claim 3, wherein said means for postprocessing comprises a digital filter.

5. The apparatus of claim 4, wherein the digital filter employs a weighting function in which different weights are applied to different digital bits or symbols.

6. A method of producing a data stream indicative of the phase of a first clock signal using a second clock signal, comprising sampling the first clock signal in accordance with the second clock signal to form a first stream of digital bits or symbols wherein a frequency ratio of the first clock signal and the second clock signal is variable throughout a range including non-integer values, each digital bit or symbol of a sequence of consecutive digital bit or symbols representing a number of transitions n of a predetermined polarity of the first clock signal that occurred during a corresponding period in a sequence of consecutive periods of the second clock signal, such that processing of the first stream of digital bits or symbols yields as the phase a digital word.

7. The method of claim 6, wherein a frequency difference phase calculation is employed, comprising:

filtering the first stream of digital bits or symbols to obtain an average ratio of frequencies of the first and second clock signals;

filtering the first stream of digital bits or symbols to obtain a series of short-term estimates of the ratio of frequencies of the first and second clock signals;

for each estimate, calculating a difference between the estimate and the average ratio of frequencies and converting the difference to phase increment; and

accumulating the phase increments to produce a running phase estimate.

8. The method of claim 6, wherein a pre-summation difference phase calculation is employed, comprising:

producing a first stream of digital words by subtracting from each said digital bit or symbol a ratio of frequencies of the first and second clock signals;

producing a second stream of digital words by accumulating the first stream of digital words; and

filtering the second stream of digital words.

9. The method of claim 6, comprising the steps of:

producing a second stream of digital bits or symbols that result when a reference clock signal is sampled in accordance with said second clock signal;

subtracting bits or symbols of the second stream of digital bits or symbols from digital bits or symbols of the first stream to produce a third stream of digital bits or symbols; and

accumulating the third stream of digital bits or symbols to form a fourth stream of digital bits or symbols each having one of the values 1, 0 and −

1.

10. The method of claim 9, wherein an integer difference phase calculation method is employed, comprising filtering the fourth stream of digital bits or symbols.

11. The method of claim 9, wherein a clock measure phase calculation is employed, comprising:

filtering said first stream of digital bits or symbols to produce a first stream of digital words;

producing a second stream of digital words that result when said reference clock signal is Sigma-Delta modulated in accordance with said second clock signal;

forming a third stream of digital words by subtracting from digital bits or symbols of said fourth stream of digital bits or symbols respective fractional portions of digital words of said second stream of digital words; and

combining said stream of digital words and said second stream of digital words.

12. The method of claim 11, wherein filtering is performed using a hyperbolic weighting function.

13. A circuit for producing a data stream indicative of the phase of a first clock signal using a second clock signal, comprising a first input terminal to which the first clock signal is applied, a second input terminal to which the second clock signal is applied, wherein a frequency ratio of the first clock signal and the second clock signal is variable throughout a range including non-integer values, and producing as an output signal a stream of digital bits or symbols, each digital bit or symbol of a sequence of consecutive digital bits or symbols representing a number of transitions n of a predetermined polarity of the first clock signal that occurred during a corresponding period in a sequence of consecutive periods of the second clock signal, such that processing of the stream of digital bits or symbols yields as the phase a digital word.

14. The circuit of claim 13, further comprising:

a weight generator;

a first accumulator; and

a second accumulator;

wherein the first accumulator receives as an input the stream of digital bits or symbols and produces an output stream of digital symbols or words, the weight generator produces a series of weights, and the second accumulator receives the series of weights and the output stream of digital words and produces a phase estimate.

15. The circuit of claim 14, wherein the second accumulator comprises a hardware multiplier.

16. The circuit of claim 14, wherein said first accumulator comprises a reference pattern generator and said output stream consists of the symbols 1, 0 and −

1, and wherein said second accumulator comprises an adder/subtractor.

17. The circuit of claim 13, further comprising:

a weight generator;

a first accumulator;

a second accumulator; and

a summation block;

wherein the weight generator produces a series of weights, the first accumulator receives as inputs the stream of digital bits or symbols and the series of weights and produces an output stream of digital words, the second accumulator receives as inputs the stream of digital bits or symbols and produces a second output stream of digital symbols, and the summation block sums outputs from the first accumulator and the second accumulator to produce a phase estimate.