Multiple load miss handling in a cache memory system

• US 6,269,427 B1
• Filed: 03/18/1999
• Issued: 07/31/2001
• Est. Priority Date: 03/18/1999
• Status: Expired due to Term

• Current Assignee: International Business Machines Corporation, NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: International Business Machines Corporation
• Inventors: Kuttanna, Belliappa Manavattira, Patel, Rajesh, Snyder, Michael Dean
• Primary Examiner(s): Kim, Matthew
• Assistant Examiner(s): PEUGH, BRIAN R
• Application Number:
  US09/271,493
• Time in Patent Office: 866 Days
• Field of Search: 711/122, 711/133, 711/137, 711/140, 711/118, 711/146, 711/130, 711/123, 711/125, 711/126
• US Class Current: 711/140
• CPC Class Codes: G06F 12/0831 using a bus scheme, e.g. with bus monitoring or watching means
• CPC Class Codes: G06F 12/0859 with reload from main memory
• CPC Class Codes: G06F 9/30043 LOAD or STORE instructions; Clear instruction
• CPC Class Codes: G06F 9/30047 Prefetch instructions; cache control instructions
• CPC Class Codes: G06F 9/30181 Instruction operation extension or modification
• CPC Class Codes: G06F 9/3824 Operand accessing
• CPC Class Codes: G06F 9/3858 Result writeback, i.e. updating the architectural state or memory

Abstract

A cache memory system including a cache memory configured for coupling to a load/store unit of a CPU, a buffer unit coupled to said cache memory, and an operation queue comprising a plurality of entries, wherein each valid operation queue entry points to an entry in the buffer unit. The buffer unit includes a plurality of data buffers and each of the data buffers is associated with a corresponding address tag. The system is configured to initiate a data fetch transaction and allocate an entry in the buffer unit in response to a CPU load operation that misses in both the cache memory and the buffer unit. The cache system is further configured to allocate entries in the operation queue in response to subsequent CPU load operations that miss in the cache memory but hit in the buffer unit prior to completion of the data fetch. Preferably, the system is configured to store the fetched data in the buffer unit entry upon satisfaction of said data fetch and still further configured to satisfy pending load operations in the operation queue from the buffer unit entry. In the preferred embodiment, the system is configured to reload the. cache memory from the buffer unit entry upon satisfying all operation queue entries pointing to the buffer unit entry and, thereafter, to invalidate the buffer unit entry and the operation queue entries. The buffer unit entries preferably each include data valid bits indicative of which portions of data stored in a buffer unit entry are valid.

Claims

1. A cache system, comprising:

a cache memory configured for coupling to a load/store unit of a central processing unit;

a buffer unit coupled to said cache memory, wherein the buffer unit comprises a plurality of data buffers, each of the data buffers associated with a corresponding address tag;

an operation queue comprising a plurality of entries, wherein each valid operation queue entry points to an entry in the buffer unit;

wherein the cache system is configured to initiate a data fetch transaction and allocate an entry in the buffer unit in response to a central processing unit load operation that misses in both the cache memory and the buffer unit, and wherein the cache system is further configured to allocate entries in the operation queue in response to subsequent central processing unit load operations related to the initial load operation that miss in the cache memory but hit in the buffer unit prior to satisfaction of the data fetch.

2. The system of claim 1, further configured to store the fetched data in the buffer unit entry upon satisfaction of said data fetch and still further configured to satisfy the subsequent load operations from the buffer unit entry.

3. The system of claim 2, further configured to reload the cache memory from the buffer unit entry upon satisfying all operation queue entries pointing to the buffer unit entry and, thereafter, to invalidate the buffer unit entry and the operation queue entries.

4. The system of claim 1, wherein the buffer unit entries include data valid bits indicative of which portions of data stored in a buffer unit entry are valid.

5. The system of claim 1, wherein said cache memory comprises a data cache memory.

6. The system of claim 1, wherein the data buffers in the buffer unit are suitable for storing one cache line of data.

7. The system of claim 1, further wherein the data fetch comprises fetching data from a system memory.

8. The system of claim 1, further wherein the data fetch comprises fetching data from a lower level cache memory.

9. A method of managing a cache memory system, comprising:

initiating a data fetch and allocating an entry in a buffer unit in response to a first central processing unit load operation that misses in both a cache memory and the buffer unit;

allocating entries in an operation queue in response to at least one subsequent central processing unit load operation related to the initial load operation that misses in the cache memory but hits in the buffer unit prior to completion of the data fetch, wherein the operation queue entries point to the corresponding buffer unit entry;

upon completion of the data fetch, loading the fetched data in the buffer unit entry and satisfying the subsequent load operations from the buffer unit entry.

10. The method of claim 9, further comprising, upon satisfying the subsequent load operations, reloading the cache memory from the buffer unit entry and invalidating the buffer unit entry and operation queue entries.

11. The method of claim 9, further comprising updating data valid bits upon completion of the data fetch wherein the data valid bits indicate which portions of the buffer unit entry are valid.

12. The method of claim 11, further comprising, prior to satisfying the subsequent operations from the buffer unit entry, comparing the data valid bits with the portions of the buffer unit entry required to satisfy the subsequent operations and suspending satisfaction of the subsequent operations from the buffer unit entry if the required portions are not valid.

13. The method of claim 9, wherein the reloading of the cache memory from the buffer unit entry and the satisfying of the subsequent load operations from the buffer unit entry proceed concurrently.

14. The method of claim 9, further comprising the central processing unit issuing additional load/store operations to the cache memory while the subsequent operations are being satisfied from the buffer unit entry.

15. The method of claim 9, wherein the data fetch comprises fetching data from a system memory.

16. The method of claim 9, wherein the data fetch comprises fetching data from a lower level cache memory.

17. The method of claim 9, wherein the data fetch comprises fetching sufficient data to fill a cache line of the cache memory.

18. A computer system, comprising:

a central processing unit;

a cache memory coupled to a load/store unit of the central processing unit;

a buffer unit coupled to said cache memory, wherein the buffer unit comprises a plurality of data buffers, each of the data buffers associated with a corresponding address tag;

an operation queue comprising a plurality of entries, wherein each valid operation queue entry points to an entry in the buffer unit; and

wherein the cache system is configured to initiate a data fetch and allocate an entry in the buffer unit in response to a central processing unit load operation that misses in both the cache memory and the buffer unit, and wherein the cache system is further configured to allocate entries in the operation queue in response to subsequent central processing unit load operations related to the initial load operation that miss in the cache memory but hit in the buffer unit prior to satisfaction of the data fetch.

19. The system of claim 18, further configured to store the fetched data in the buffer unit entry upon satisfaction of said data fetch and still further configured to satisfy the subsequent load operations from the buffer unit entry.

20. The system of claim 19, further configured to reload the cache memory from the buffer unit entry upon satisfying all operation queue entries pointing to the buffer unit entry and, thereafter, invalidating the buffer unit entry and the operation queue entries.