Method of manufacturing a thin film solar battery module

• US 6,271,053 B1
• Filed: 11/04/1999
• Issued: 08/07/2001
• Est. Priority Date: 03/25/1999
• Status: Expired due to Term

• Current Assignee: Kaneka Corporation
• Original Assignee: Kaneka Corporation
• Inventors: Kondo, Masataka
• Primary Examiner(s): Bowers, Charles
• Assistant Examiner(s): SARKAR, ASOK K
• Application Number:
  US09/433,905
• Time in Patent Office: 642 Days
• Field of Search: 136/244, 136/258, 136/290, 438/96, 438/98, 438/608, 438/642, 438/652, 438/57
• US Class Current: 438/57
• CPC Class Codes: H01L 31/046 PV modules composed of a plurality of thin film solar cells deposited on the same substrate
• CPC Class Codes: H01L 31/048 Encapsulation of modules
• CPC Class Codes: H01L 31/1824 Special manufacturing methods for microcrystalline Si, uc-Si
• CPC Class Codes: H01L 31/204 including AIVBIV alloys, e.g. SiGe, SiC
• CPC Class Codes: Y02E 10/545 Microcrystalline silicon PV cells
• CPC Class Codes: Y02P 70/50 Manufacturing or production processes characterised by the final manufactured product
• CPC Class Codes: Y10S 136/29 Testing, calibrating, treating, e.g. aging

Abstract

A method of manufacturing an integrated thin film solar battery module including a substrate, and a plurality of unit cells connected in series on the substrate, each of the unit cells having a first electrode layer, a semiconductor layer and a second electrode layer which are stacked one upon the other on the substrate. The method includes the steps of scribing the first electrode layer formed on the substrate, forming a semiconductor layer on the first electrode layer, scribing the semiconductor layer for each of the plurality of unit cells to form openings for connection to the first electrode layer, forming a second electrode layer on the semiconductor layer, scribing the second electrode layer and the semiconductor layer in the vicinity of the openings formed in the semiconductor layer, allowing an edge surface of the semiconductor layer to be exposed to the outside by removing residues of the second electrode layer and the semiconductor layer, and applying a heat treatment at 130° C. or higher after division of the second electrode layer and the semiconductor layer.

Claims

1. A method of manufacturing an integrated thin film solar battery module comprising a substrate, and a plurality of unit cells connected in series on the substrate, each of said unit cells comprising a first electrode layer, a semiconductor layer and a second electrode layer which are stacked one upon the other on the substrate, said method comprising the steps of:

partly removing the first electrode layer formed on the substrate to divide the first electrode layer corresponding to the plurality of unit cells;

forming a semiconductor layer on the first electrode layer;

partly removing the semiconductor layer for each of a plurality of unit cells to form openings for connection to the first electrode layer;

forming a second electrode layer on the semiconductor layer;

partly removing the second electrode layer and the semiconductor layer in the vicinity of the openings formed in the semiconductor layer so as to divide the second electrode layer and the semiconductor layer corresponding to the plurality of unit cells;

allowing an edge surface of the semiconductor layer to be exposed to the outside by removing residues of the second electrode layer and the semiconductor layer; and

applying a heat treatment at 130°

C. or higher after division of the second electrode layer and the semiconductor layer, wherein said heat treatment is carried out for a time sufficient to make a fresh surface of the semiconductor layer nonconductive.

2. The method according to claim 1, wherein said heat treatment is carried out at a temperature not lower than 150°

C. and lower than the temperature for forming the semiconductor layer.

3. The method according to claim 1, wherein said heat treatment is carried out at 150°

C. for at least 20 minutes.

4. The method according to claim 1, wherein said heat treatment is carried out at 160°

C. for at least 15 minutes.

5. The method according to claim 1, wherein said heat treatment is carried out on the basis of a straight line joining a point corresponding to the condition of 150°

C. and 20 minutes and another point corresponding to the condition of 160°

C. and 15 minutes depicted on a coordinate system assigning a reciprocal of the absolute temperature on the abscissa and a logarithm of reciprocal of time on the ordinate, and wherein the heat treating time is determined to be longer than a time positioned on the straight line at a predetermined heat treating temperature.

6. The method according to claim 1, wherein said heat treatment is carried out under an air atmosphere.

7. The method according to claim 1, further comprising the step of laminating a resin sheet on the back surface of said unit cells and thermally curing said resin sheet for encapsulating the unit cells.

8. The method according to claim 1, further comprising the step of laminating a resin sheet on the back surface of said unit cells and thermally curing said resin sheet for encapsulating the unit cells, wherein said heat treatment is carried out in the step of the thermal curing of said resin sheet.

9. The method according to claim 1, further comprising the step of applying a reverse bias voltage to said unit cells so as to remove defects after said heat treatment.

10. The method according to claim 1, wherein a part of said first electrode, a part of said semiconductor layer and a part of said second electrode are removed by means of laser beam irradiation.

11. The method according to claim 10, wherein the laser beam irradiation is performed around room temperature.

12. The method according to claim 1, wherein said semiconductor layer contains silicon as a main component.

13. The method according to claim 1, wherein said first electrode comprises a transparent conductive oxide.

14. The method according to claim 1, wherein said second electrode comprises a metal, a laminate comprising at least two metal layers or a laminate comprising a transparent conductive oxide layer and a metal layer.