Process of fabricating a chip scale surface mount package for semiconductor device

• US 6,271,060 B1
• Filed: 09/13/1999
• Issued: 08/07/2001
• Est. Priority Date: 09/13/1999
• Status: Expired due to Term

• Current Assignee: Vishay Intertechnology Incorporated
• Original Assignee: Vishay Intertechnology Incorporated
• Inventors: Zandman, Felix, Ho, Yueh-Se, Kasem, Y. Mohammed
• Primary Examiner(s): Bowers, Charles
• Assistant Examiner(s): Huynh, Yennhu B.
• Application Number:
  US09/395,095
• Time in Patent Office: 694 Days
• Field of Search: 438/113, 438/109, 438/114, 438/118, 438/119, 438/465, 438/133, 438/135-138, 438/268, 438/589, 438/455, 438/458, 438/460, 438/464, 257/678, 257/626, 257/621, 257/508, 257/786
• US Class Current: 438/113
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06551 Conductive connections on the side of the device
• CPC Class Codes: H01L 2225/06586 Housing with external bump or bump-like connectors
• CPC Class Codes: H01L 23/49805 the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/12044 OLED

Abstract

This semiconductor surface mount package is relatively inexpensive to produce and has a footprint that is essentially the same size as the die. A conductive substrate is attached to the back side of a wafer and is in electrical contact with a terminal on the back side of each die in the wafer. A nonconductive overcoat is formed and patterned on the front side of the wafer, leaving a portion of the passivation layer and the connection pads for the dice exposed, each of the connection pads being coated with a solderable metal layer. The assembly is then sawed in perpendicular directions along the scribe lines between the dice, but the saw cuts do not extend all the way through the substrate, which remains intact at its back side. The parallel cuts in one direction are broken to produce die strips which are mounted, sandwich-like, in a stack, with one side of the strips exposed. A metal layer is sputtered or evaporated on one side of the stack; the stack is turned over and a similar process is performed on the other side of the stack. The resulting metal layers are deposited on front side of the die and extend along the edges of the die to the edges and back side of the substrate. The metal is not deposited on the surfaces of the overcoat. The strips in the stack are then separated, and the saw cuts in the perpendicular direction are broken to separate the individual dice. A thick metal layer is plated on the sputtered or evaporated layers to establish a good electrical connection between the front side and the terminal on the back side of each die. The resulting package thus includes a metal layer which wraps around the edges of the die to form an electrical connection between a location on the front side of the die and the conductive substrate. The package is essentially the same size as the die. In an alternative embodiment, a nonconductive substrate is used and vias are formed in the substrate and filled with metal to make electrical contact with the terminal on the back side of the die.

Claims

1. A process of fabricating a package for a semiconductor device comprising:

providing a semiconductor wafer including a plurality of dice;

forming an overcoat on a surface on a front side of the wafer;

patterning the overcoat to expose a connection pad on a front side of the dice;

attaching the wafer to a substrate;

separating the wafer into multichip strips, each strip containing a plurality of dice;

assembling the strips sandwich-like to form a stack, with an edge of each die in the stack being exposed;

depositing at least a first metal layer on one side of the stack, the first metal layer wrapping around an edge of a die to form an electrical connection between a location on the front side of the die and a device terminal on a back side of the die;

disassembling the stack into individual strips; and

separating a strip into individual dice.

2. The process of claim 1 comprising depositing at least a second metal layer on an opposite side of the stack, the second metal layer wrapping around an opposite edge of the die to form an electrical connection between a second location on the front side of the die and the device terminal on the back side of the die.

3. The process of claim 1 wherein separating the wafer into strips comprises:

cutting through the wafer and through a portion of the substrate along a first set of parallel lines between the dice to form a first set of partial cuts, the substrate remaining intact at a back side of the substrate; and

breaking the substrate along the partial cuts.

4. The process of claim 3 wherein cutting comprises sawing.

5. The process of claim 3 wherein cutting comprises photolithographic patterning and etching.

6. The process of claim 3 further comprising cutting through the wafer and through a portion of the substrate between dice along a second set of lines perpendicular to the first set of parallel lines to form a second set of partial cuts before separating the wafer into strips.

7. The process of claim 6 wherein separating a strip into individual dice comprises breaking the strip along the second set of partial cuts.

8. The process of claim 6 wherein the first set of partial cuts is deeper than the second set of partial cuts.

9. The process of claim 1 wherein depositing at least a first metal layer comprises sputtering.

10. The process of claim 1 wherein depositing at least a first metal layer comprises evaporation.

11. The process of claim 1 wherein depositing the first metal layer comprises depositing a first metal sublayer and depositing second metal sublayer over the first metal sublayer.

12. The process of claim 11 wherein depositing the second metal sublayer comprises plating.

13. The process of claim 1 wherein the connection pad located in an interior region of the front side of the die, and wherein assembling the strips to form a stack comprises sealing off the connection pad.

14. The process of claim 1 comprising forming a solder ball in electrical contact with the connection pad.

15. The process of claim 1 wherein the substrate is electrically conductive.

16. The process of claim 15 wherein attaching the wafer to a substrate comprises attaching the wafer to the substrate with an electrically conductive cement.

17. The process of claim 1 wherein the substrate is electrically nonconductive.

18. The process of claim 17 further comprising forming a via entirely through the substrate and filling the via with an electrically conductive material.

19. The process of claim 1 further comprising depositing at least one layer of a solderable metal on the first connection pad.

20. The process of claim 19 further comprising removing an oxide layer before depositing the layer of solderable metal.

21. The process of claim 1 wherein the semiconductor device comprises a MOSFET.

22. The process of claim 1 wherein the semiconductor device comprises a diode.

23. The process of claim 1 wherein the semiconductor device comprises a JFET.

24. The process of claim 1 wherein the semiconductor device comprises a bipolar transistor.

25. The process of claim 1 wherein the semiconductor device comprises an IC.

26. A process of fabricating a package for a semiconductor device comprising:

providing a semiconductor wafer including a plurality of dice;

attaching a front side of the wafer to a first substrate;

processing the back side of the wafer so as to thin the wafer;

creating openings in the first substrate to expose connection pads on a front side of the dice;

attaching a back side of the wafer to a second substrate to form a sandwich containing the wafer interposed between the first and second substrates;

separating the sandwich into strips, each strip containing a plurality of dice;

assembling the strips together to form a stack, with one edge of each die being exposed;

depositing at least a first metal layer on one side of the stack, the first metal layer wrapping around an edge of a die to form an electrical connection between a location on the front side of the die and a terminal on a back side of the die;

disassembling the stack into individual strips; and

separating a strip into individual dice.

27. The process of claim 26 wherein processing the back side of the wafer comprises grinding.

28. The process of claim 26 wherein processing the back side of the wafer comprises lapping.

29. The process of claim 26 wherein processing the back side of the wafer comprises etching.

30. A process of fabricating a package for a semiconductor device comprising:

providing a semiconductor wafer including a plurality of dice;

attaching the wafer to a substrate;

forming an overcoat on a surface of the wafer;

patterning the overcoat to expose connection pads on a front side of the dice;

separating the wafer into multichip strips, each strip containing a plurality of dice;

forming an electrically conductive wraparound layer, the wraparound layer wrapping around an edge of the die to form at least a portion of an electrical path between a location on a front side of the die and a device terminal at a back side of the die; and

separating the wafer into individual dice.

31. The process of claim 30 wherein the wraparound layer comprises a conductive polymer.

32. The process of claim 30 wherein the wraparound layer comprises a metal.

33. A process of forming an electrical connection between a location on a front side of a semiconductor die and a device terminal at a back side of the die comprising depositing at least one metal layer extending from the location on the front die of the die and around an edge of the die, the at least one metal layer forming at least a portion of an electrical path between the location on the front side of the die and the device terminal at the back side of the die.

34. The process of claim 33 comprising attaching a conductive substrate to the back side of the die, the at least one metal layer being in contact with the substrate.

35. A process of fabricating a package for a vertical power MOSFET comprising:

providing a semiconductor wafer including a plurality of dice;

attaching a back side of the wafer to a conductive substrate;

forming a nonconductive overcoat on a front side of the dice;

patterning the overcoat to expose source and gate pads on the front side of the dice;

separating the wafer into strips, each strip containing a plurality of dice;

assembling the strips sandwich-like to form a stack, with an edge of each die in the stack being exposed;

depositing a first metal layer on one side of the stack, the first metal layer wrapping around an edge of each die to form an electrical connection between a location on the front side of the die and a drain terminal of the MOSFET;

disassembling the stack into individual strips; and

plating a second metal layer over the first metal layer.