Method of fabricating a mixed circuit capacitor

• US 6,271,082 B1
• Filed: 04/25/2000
• Issued: 08/07/2001
• Est. Priority Date: 03/17/2000
• Status: Expired due to Term

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Hou, Chia-Hsin, Lin, Jyh-Kuang, Ko, Joe, Jung, Tz-Guei
• Primary Examiner(s): CHAUDHARI, CHANDRA P
• Application Number:
  US09/557,345
• Time in Patent Office: 469 Days
• Field of Search: 438/239, 438/241, 438/250, 438/253, 438/393, 438/396, 438/634, 438/637
• US Class Current: 438/250
• CPC Class Codes: H01L 21/3212 by chemical mechanical polishing [CMP]
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 28/55 with a dielectric comprising a perovskite structure material
• CPC Class Codes: H01L 28/60 Electrodes

Abstract

A method for fabricating a capacitor is applicable to a fabrication process for a mixed circuit. The method involves forming a first dielectric layer, a stop layer, and a second dielectric layer on a substrate having a conductive region. A first opening is then formed in the second dielectric layer, followed by forming a second opening in the stop layer and the first dielectric layer, so that the first opening and the second opening form a dual damascene opening for exposing the conductive region. The dual damascene opening is filled with a first conductive layer, so as to form a via plug and a lower electrode of the capacitor for connecting to the conductive region. A third dielectric layer, which is located between the lower electrode and a subsequent formed upper electrode, is then formed over the substrate, so that the lower electrode and a part of the second dielectric layer adjacent to the lower electrode are completely covered by the third dielectric layer. A patterned second conductive layer is formed on a part of the third dielectric layer, whereby an upper electrode for completely covering the lower electrode is formed.

Claims

1. A fabrication method for a capacitor, applicable to a fabrication process for a mixed circuit, the method comprising:

providing a substrate, said substrate having a conductive region;

forming a first dielectric layer on the substrate;

forming a stop layer on the first dielectric layer;

forming a second dielectric layer on the stop layer;

forming a first opening in the second dielectric layer, and forming a second opening in the stop layer and the dielectric layer, wherein the first opening and the second opening form a dual damascene opening for exposing the conductive region;

filling the dual damascene opening with a first conductive layer so as to form a via plug and a lower electrode for connecting to the conductive region;

forming a patterned third dielectric layer on the lower electrode and a portion of the second dielectric layer; and

forming a patterned second conductive layer on a part of the third dielectric layer whereby an upper electrode is formed, said upper electrode completely covering the lower electrode.

2. The fabrication method of claim 1, wherein the conductive region includes an active region.

3. The fabrication method of claim 1, wherein the conductive region includes a polysilicon layer.

4. The fabrication method of claim 1, wherein the conductive region includes a metal layer.

5. The fabrication method of claim 1, wherein the method for forming the dual damascene opening further comprising:

patterning the second dielectric layer using a photolithographic and etching process so as to form first opening, said first opening exposing the stop layer and is located above the conductive region; and

patterning the first dielectric layer using a photolithographic and etching process, so as to form a second opening, said second opening exposing the conductive region.

6. The fabrication method of claim 1, wherein the step of filling the dual damascene opening with a first conductive layer comprising:

forming a first conductive material for covering a profile of the dual damascene opening and the second dielectric layer; and

removing a portion of the first conductive layer on the second dielectric layer.

7. The fabrication method of claim 6, wherein the step of removing a portion of the first conductive layer on the second dielectric layer includes chemical mechanical polishing (CMP).

8. The fabrication method of claim 6, wherein the first conductive material includes metal.

9. The fabrication method of claim 8, further includes forming a conformal barrier layer for covering a profile of the dual damascene opening and the second dielectric layer before the step of forming metal in the dual damascene opening.

10. The fabrication method of claim 9, wherein the metal includes tungsten and the barrier layer includes titanium nitride.

11. The fabrication method of claim 1, wherein the step of forming the upper electrode comprising:

forming a second conductive layer on the substrate; and

patterning the second conductive material using a photolithographic and etching process so as to form the upper electrode, wherein the upper electrode has a projection area larger than that of the lower electrode.

12. The fabrication method of claim 1, wherein the stop layer includes silicon nitride.

13. A fabrication method for a mixed circuit, comprising:

providing a substrate, said substrate having a first conductive region and a second conductive region;

forming a first dielectric layer on the substrate;

forming a stop layer on the first dielectric layer;

forming a second dielectric layer on the stop layer;

forming a first opening in the second dielectric layer, said first opening is on the first conductive region;

forming a second opening in the stop layer and the dielectric layer, wherein the first opening and the second opening form a dual damascene opening for exposing said first conductive region;

forming a third opening in the second dielectric layer, the stop layer, and the first dielectric layer, said third opening exposing the second conductive region;

filling the dual damascene opening and the third opening with a first conductive layer so as to form both a via plug for connecting to the first conductive region and a lower electrode and a second via plug for connecting the second conductive region;

forming a patterned third dielectric layer on the substrate, said patterned third dielectric layer completely covering the lower electrode and a portion of the second dielectric layer adjacent to the lower electrode;

forming a patterned second conductive layer on a part of the third dielectric layer whereby an upper electrode is formed, said upper electrode completely covering the lower electrode;

forming a patterned third conductive layer on the substrate, said third conductive layer connecting to the second via plug.

14. The fabrication method of claim 13, wherein the method for forming the first opening, the second opening, and the third opening further comprising:

patterning the second dielectric layer using a first photolithographic and etching process so as to form first opening, said first opening exposing the stop layer and is located above the first conductive region; and

patterning the second dielectric layer, the stop layer, and the first dielectric layer using a second photolithographic and etching process, so as to form the second opening and the third opening.

15. The fabrication method of claim 13, wherein the method for forming the first via plug, the lower electrode, and the second via plug comprising:

forming a first conductive material for covering a profile of the dual damascene opening, the third opening, and the second dielectric layer; and

removing a portion of the first conductive layer on the second dielectric layer.

16. The fabrication method of claim 15, wherein the step of removing a portion of the first conductive layer on the second dielectric layer includes chemical mechanical polishing (CMP).

17. The fabrication method of claim 16, wherein the first conductive material includes metal.

18. The fabrication method of claim 17, further includes forming a conformal barrier layer in the dual damascene opening and the third opening and on the second dielectric layer before the step of forming the first conductive material in the dual damascene opening.

19. The fabrication method of claim 18, wherein the first conductive material includes tungsten and the conformal barrier layer includes titanium nitride.

20. The fabrication method of claim 13, wherein the step of forming the upper electrode and the patterned third dielectric layer comprising:

forming a second conductive layer on the substrate; and

patterning the second conductive material using a photolithographic and etching process so as to form the upper electrode and the patterned third dielectric layer, wherein the upper electrode has a projection area larger than that of the lower electrode.