Method of making MOSFET with high dielectric constant gate insulator and minimum overlap capacitance
First Claim
1. A method of forming a MOSFET device having low overlap capacitance and a short channel length comprising the steps of:
- (a) providing a semiconductor structure having a film stack formed on a surface of a substrate, said film stack comprising at least a pad oxide layer formed on said surface of said substrate and a nitride layer formed on said pad oxide layer;
(b) forming a gate hole in said nitride layer stopping on said pad oxide layer;
(c) forming an oxide layer on said nitride layer in said gate hole;
(d) etching said oxide layer and a portion of said pad oxide layer so as to provide an opening in said gate hole exposing said substrate, wherein the pad oxide layer is tapered by said etching;
(e) forming a high-k, high-temperature metal oxide layer about said gate hole and on said exposed substrate;
(f) filling said gate hole with gate conductor;
(g) removing said nitride layer exposing portions of said high-k, high-temperature metal oxide; and
(h) completing fabrication of said MOSFET device.
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Abstract
Methods of fabricating metal oxide semiconductor field effect transistor (MOSFET) devices having a high dielectric constant (k greater than 7) gate insulator, low overlap capacitance (0.35 fF/μm or below) and a channel length (sub-lithographic, e.g., 0.1 μm or less) that is shorter than the lithography-defined gate lengths are provided. The methods include a damascene processing step and a chemical oxide removal (COR) step. The COR step produces a large taper on a pad oxide layer which, when combined with a high-k gate insulator, results in low overlap capacitance, sort channel lengths and better device performance as compared to MOSFET devices that are formed using conventional Complementary Metal Oxide Semiconductor (CMOS) technologies.
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Citations
31 Claims
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1. A method of forming a MOSFET device having low overlap capacitance and a short channel length comprising the steps of:
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(a) providing a semiconductor structure having a film stack formed on a surface of a substrate, said film stack comprising at least a pad oxide layer formed on said surface of said substrate and a nitride layer formed on said pad oxide layer;
(b) forming a gate hole in said nitride layer stopping on said pad oxide layer;
(c) forming an oxide layer on said nitride layer in said gate hole;
(d) etching said oxide layer and a portion of said pad oxide layer so as to provide an opening in said gate hole exposing said substrate, wherein the pad oxide layer is tapered by said etching;
(e) forming a high-k, high-temperature metal oxide layer about said gate hole and on said exposed substrate;
(f) filling said gate hole with gate conductor;
(g) removing said nitride layer exposing portions of said high-k, high-temperature metal oxide; and
(h) completing fabrication of said MOSFET device. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 27)
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16. A method of forming a MOSFET device having low overlap capacitance and a short channel length comprising the steps of:
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(i) providing a semiconductor structure having a dummy film stack formed on a surface of a substrate, said dummy film stack comprising at least a pad oxide layer formed on said surface of said substrate, a polysilicon layer on said pad oxide layer, and a SiO2 layer formed on said polysilicon layer;
(ii) removing selective portions of said dummy film stack stopping on said pad oxide layer so as to provide a patterned dummy gate region;
(iii) removing said SiO2 layer from said patterned dummy gate region;
(iv) forming activated source/drain extensions in said substrate beneath said dummy gate region;
(v) forming spacers on sidewalls of said dummy gate region;
(vi) forming activated source/drain regions in said substrate;
(vii) forming silicide regions in portions of said pad oxide layer and in said polysilicon layer of said dummy gate region;
(viii) forming an insulator layer surrounding said dummy gate region;
(ix) planarizing said insulator layer stopping at said polysilicon layer in said dummy gate region;
(x) forming an opening so as to expose a portion of said substrate, said opening being formed by removing said polysilicon layer of said dummy gate and by tapering a portion of said pad oxide layer of said dummy gate;
(xi) forming a high-k, low-temperature metal oxide in said opening; and
(xii) filling said opening with a gate conductor deposited at low temperatures. - View Dependent Claims (17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 28, 29, 30, 31)
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Specification