Direct build-up layer on an encapsulated die package

• US 6,271,469 B1
• Filed: 11/12/1999
• Issued: 08/07/2001
• Est. Priority Date: 11/12/1999
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Ma, Qing, Fujimoto, Harry, Mu, Chun
• Primary Examiner(s): BERHANE, ADOLF D
• Application Number:
  US09/438,221
• Time in Patent Office: 634 Days
• Field of Search: 174/52.1, 174/52.2, 174/52.3, 174/52.4, 361/813, 257/676, 257/693, 257/738, 257/778, 257/787, 257/788, 257/789, 298/32, 298/40
• US Class Current: 174/521
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/20 Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 2224/211 Disposition
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/92244 the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/4334 Auxiliary members in encapsulations H01L23/49568 takes precedence
• CPC Class Codes: H01L 23/485 consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts H01L23/4821, H01L23/4822, H01L23/4824, H01L23/4825 take precedence; materials H01L23/532, bond pads H01L24/02, bump connectors H01L24/10
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/96 the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01042 : Molybdenum [Mo]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15174 : in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/18162 : of a chip with build-up interconnect
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H01L 2924/351 : Thermal stress

Abstract

A microelectronic package including a microelectronic die having an active surface and at least one side. An encapsulation material is disposed adjacent the microelectronic die side(s), wherein the encapsulation material includes at least one surface substantially planar to the microelectronic die active surface. A first dielectric material layer may be disposed on at least a portion of the microelectronic die active surface and the encapsulation material surface. At least one conductive trace is then disposed on the first dielectric material layer. The conductive trace(s) is in electrical contact with the microelectronic die active surface. At least one conductive trace extends vertically adjacent the microelectronic die active surface and vertically adjacent the encapsulation material surface.

Claims

1. A microelectronic package, comprising:

a microelectronic die having an active surface and at least one side;

encapsulation material adjacent said at least one microelectronic die side, wherein said encapsulation material includes at least one surface substantially planar to said microelectronic die active surface;

a first dielectric material layer disposed on at least a portion of said microelectronic die active surface and said encapsulation material surface; and

at least one conductive trace disposed on said first dielectric material layer and in electrical contact with said microelectronic die active surface, wherein said at least one conductive trace extends vertically adjacent said microelectronic die active surface and vertically adjacent said encapsulation material surface.

2. The microelectronic package of claim 1, further including at least one additional dielectric material layer disposed over said at least on conductive trace and said first dielectric material layer.

3. The microelectronic package of claim 2, wherein at least a portion of said at least one conductive trace extends through and resides on said at least one additional dielectric material layer.

4. The microelectronic package of claim 1, wherein said microelectronic die further includes a back surface;

and further including at least one heat dissipation device in thermal contact with said microelectronic die back surface.

5. A method of fabricating a microelectronic package, comprising:

providing at least one microelectronic die having an active surface and at least one side;

abutting a protective film against said at least one microelectronic die active surface;

encapsulating said at least one microelectronic die with an encapsulation material adjacent said at least one microelectronic die side, wherein said encapsulating material provides at least one surface of said encapsulation material substantially planar to said microelectronic die active surface; and

removing said protective film.

6. The method of claim 5, further including:

forming at least one dielectric material layer on at least a portion of said microelectronic die active surface and said encapsulation material surface;

forming a via through said at least one dielectric material layer to expose a portion of said microelectronic die active surface; and

forming at least one conductive trace on said at least one dielectric material layer which extends into said via to electrically contact said microelectronic die active surface, wherein said at least one conductive trace extends vertically adjacent said microelectronic die active surface and vertically adjacent said encapsulation material surface.

7. The method of claim 5, further including forming at least one additional dielectric material layer disposed over said at least on conductive trace and said at least one dielectric material layer.

8. The method of claim 7, wherein forming said at least one conductive trace on said at least one dielectric layer further includes forming at least a portion of said at least one conductive trace to extend through and reside on said at least one additional dielectric material layer.

9. The method of claim 5, further including thermally contacting a heat dissipation device with a back surface of said microelectronic die.

10. A method of fabricating a microelectronic package, comprising:

providing an adhesive protective film suspended on a substantially rigid frame;

attaching an active surface of at least one microelectronic die to said adhesive film;

encapsulating said at least one microelectronic die with an encapsulation material adjacent at least one side of said microelectronic die, wherein said encapsulating material provides at least one surface of said encapsulation material substantially planar to said microelectronic die active surface; and

removing said adhesive protective film.

11. The method of claim 10, further including:

forming at least one dielectric material layer on at least a portion of said microelectronic die active surface and said encapsulation material surface;

forming a via through said at least one dielectric material layer to expose a portion of said microelectronic die active surface; and

forming at least one conductive trace on said at least one dielectric material layer which extends into said via to electrically contact said microelectronic die active surface, wherein said at least one conductive trace extends vertically adjacent said microelectronic die active surface and vertically adjacent said encapsulation material surface.

12. The method of claim 10, further including forming at least one additional dielectric material layer disposed over said at least on conductive trace and said at least one dielectric material layer.

13. The method of claim 12, wherein forming said at least one conductive trace on said at least one dielectric layer further includes forming at least a portion of said at least one conductive trace to extend through and reside on said at least one additional dielectric material layer.

14. The method of claim 10, further including thermally contacting a heat dissipation device with a back surface of said microelectronic die.

15. A method of fabricating a microelectronic package, comprising:

providing at least one microelectronic die having an active surface, a back surface, and at least one side;

attaching said at least one microelectronic die back surface to a heat dissipation device;

abutting a protective film against said at least one microelectronic die active surface;

encapsulating said at least one microelectronic die and said heat dissipation device with an encapsulation material, wherein said encapsulating material provides at least one surface of said encapsulation material substantially planar to said microelectronic die active surface; and

removing said protective film.

16. The method of claim 15, further including:

forming at least one dielectric material layer on at least a portion of said microelectronic die active surface and said encapsulation material surface;

forming a via through said at least one dielectric material layer to expose a portion of said microelectronic die active surface; and

forming at least one conductive trace on said at least one dielectric material layer which extends into said via to electrically contact said microelectronic die active surface, wherein said at least one conductive trace extends vertically adjacent said microelectronic die active surface and vertically adjacent said encapsulation material surface.

17. The method of claim 15, further including forming at least one additional dielectric material layer disposed over said at least on conductive trace and said at least one dielectric material layer.

18. The method of claim 17, wherein forming said at least one conductive trace on said at least one dielectric layer further includes forming at least a portion of said at least one conductive trace to extend through and reside on said at least one additional dielectric material layer.

19. The method of claim 15, further including thinning said at least one microelectronic die prior to attaching said at lest one microelectronic die back surface to a heat dissipation device.

20. A method of fabricating a microelectronic package, comprising:

providing an adhesive protective film suspended on a substantially rigid frame;

attaching a back surface of at least one microelectronic die to said adhesive film;

abutting a protective film against an active surface of said at least one microelectronic die;

encapsulating said at least one microelectronic die with an encapsulation material adjacent at least one side of said microelectronic die, wherein said encapsulating material provides at least one surface of said encapsulation material substantially planar to said microelectronic die active surface;

removing said protective film; and

removing said adhesive protective film.

21. A method of fabricating a microelectronic package, comprising:

providing an adhesive protective film suspended on a substantially rigid frame;

attaching a back surface of at least one microelectronic die to at least one heat dissipation device;

attaching a back surface of said at least one heat dissipation device to said adhesive film;

abutting a protective film against an active surface of said at least one microelectronic die;

encapsulating said at least one microelectronic die with an encapsulation material adjacent at least one side of said microelectronic die, wherein said encapsulating material provides at least one surface of said encapsulation material substantially planar to said microelectronic die active surface;

removing said protective film; and

removing said adhesive protective film.