Semiconductor component which can be controlled by a field effect

• US 6,271,562 B1
• Filed: 03/01/1999
• Issued: 08/07/2001
• Est. Priority Date: 02/27/1998
• Status: Expired due to Term

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Graf, Heimo, Deboy, Gerald, Stengl, Jens-Peer, Tihanyi, Jenoe
• Primary Examiner(s): Thomas, Tom
• Assistant Examiner(s): Hu, Shouxiang
• Application Number:
  US09/259,636
• Time in Patent Office: 890 Days
• Field of Search: 257/341, 257/342, 257/330, 257/331, 257/328, 257/170
• US Class Current: 257/341
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A power semiconductor component that can be controlled by a field effect has a multiplicity of parallel-connected individual components disposed in cells, the cells are disposed tightly packed on a relatively small space in a cell array. Parallel-connected source zones of the cells have shadowed regions that in each case reduce an effective W/L channel ratio in the cells containing the shadowed regions. The invention has the advantage that because of the provision of the shadowed regions inside the source zones that are preferably undoped or at least doped much weaker than the source zones, the critical regions in the cell array with the highest current density are specifically moderated. Thus the current density in the current-carrying filament of the cell is more homogeneously distributed. This measure renders it possible to reduce the cell grid spacing of the cells in the cell array, or to reduce the forward resistance per unit area, and this leads simultaneously to a reduction in the power loss.

Claims

1. In an improved power semiconductor component which can be controlled by a field effect and has a multiplicity of parallel-connected individual components disposed in each case in cells, the cells disposed tightly packed on a relatively small space in a cell array, the improvement comprising:

a semiconductor body having a surface, including;

a) at least one inner zone of a first conductivity type bordering at least partially on said surface, said at least one inner zone having at least one depletion zone of a second conductivity type and at least one complementary depletion zone having said first conductivity type a total quantity of doping of said at least one depletion zone corresponding approximately to a total quantity of doping of said at least one complementary depletion zone;

b) at least one drain zone bordering said at least one inner zone;

c) at least one base zone disposed in each of the cells and having a second conductivity type, said at least one base zone embedded in said surface;

d) at least one source zone disposed in each of the cells and having said first conductivity type, said at least one source zone embedded in said at least one base zone; and

e) shadow regions disposed in at least one of said at least one source zone of the cells, said shadow regions reducing an effective ratio of a channel width to a channel length;

at least one source electrode making contact with said at least one base zone and said at least one source zone; and

at least one gate electrode disposed above and completely insulated from said semiconductor body.

2. The power semiconductor component according to claim 1, wherein source zones of two neighboring cells have source subregions with a minimum spacing d_min between said source zones, one of said source subregions in each case having said shadowed regions.

3. The power semiconductor component according to claim 1, wherein said shadowed regions have a same conductivity type as said at least one source zone and have a lower doping concentration than said at least one source zone.

4. The power semiconductor component according to claim 1, wherein said shadowed regions are undoped.

5. The power semiconductor component according to claim 1, wherein at least one of said at least one source zone and said shadowed regions are arsenic-doped.

6. The power semiconductor component according to claim 1, wherein each of the cells has precisely one of said at least one base zone and at least one of said at least one source zone, said one base zone and said at least one source zone disposed approximately concentrically about a midpoint of a respective cell and have cross-sectional surfaces corresponding approximately to a cross-sectional surface of the respective cell.

7. The power semiconductor component according to claim 1, wherein the cells in the cell array are substantially hexagonal-shaped cells.

8. The power semiconductor component according to claim 1, wherein the cells in the cell array are substantially square-shaped cells.

9. The power semiconductor component according to claim 1, wherein said shadowed regions have a substantially propeller shape and are disposed inside a cell in a plane of said surface.

10. The power semiconductor component according to claim 1, wherein each of said at least one source zone of the cells of the cell array has shadowed regions.

11. The power semiconductor component according to claim 1, wherein the cell array has a cell grid spacing smaller than 20 uM.

12. The power semiconductor component according to claim 1, wherein said at least one drain zone has a doping of said first conductivity type.

13. The power semiconductor component according to claim 1, wherein said at least one drain zone has a substantially higher doping concentration than said at least one inner zone.

14. The power semiconductor component according to claim 1, wherein said at least one inner zone is grown at least partially epitaxially.

15. The power semiconductor component according to claim 1, wherein the cell array has a plurality of at least partially inactive cells and a multiplicity of active cells free of said shadowed regions, said multiplicity of active cells surrounded at least partially by said plurality of said at least partially inactive cells, said plurality of said at least partially inactive cells having said shadowed regions.