Semiconductor device having a carbon containing insulation layer formed under the source/drain

• US 6,271,566 B1
• Filed: 11/16/1999
• Issued: 08/07/2001
• Est. Priority Date: 03/25/1997
• Status: Expired due to Fees

• Current Assignee: Toshiba Corporation
• Original Assignee: Toshiba Corporation
• Inventors: Tsuchiaki, Masakatsu
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): PHAM, HOAI V
• Application Number:
  US09/440,958
• Time in Patent Office: 630 Days
• Field of Search: 257/77, 257/332, 257/345, 257/346, 257/347, 257/392, 257/655, 257/914, 257/374, 257/382
• US Class Current: 257/347
• CPC Class Codes: H01L 21/2236 from or into a plasma phase
• CPC Class Codes: H01L 21/26506 in group IV semiconductors
• CPC Class Codes: H01L 21/8234 MIS technology , i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells
• CPC Class Codes: Y10S 257/914 Polysilicon containing oxygen, nitrogen, or carbon, e.g. sipos

Abstract

A manufacturing method produces a semiconductor IC device which can maintain a low power consumption for electronic circuits and form gate-isolation layers of different thicknesses without increasing the manufacturing cost. The semiconductor IC device has gate-isolation layers of different thicknesses on the same semiconductor substrate surface. To form such gate-isolation layers, a silicon dioxide layer is formed in first and second regions. The dopant-concentration is adjusted in silicon dioxide layer that is to have a thickness different from the above silicon dioxide layer thickness in the second region B. A carbon-containing semiconductor layer is selectively formed in either the first region or the second region. Therefore, there is no need for additional steps for forming silicon dioxide layers of different thicknesses in the first region and in the second region. In addition, a carbon-containing semiconductor layer is selectively formed on desired areas of the semiconductor substrate where thinner oxide layer is to be formed. The semiconductor substrate is oxidized successively to have oxide layers of different thickness on the surface of the substrate in one step.

Claims

1. A semiconductor device comprising:

a semiconductor substrate;

a plurality of isolation regions formed on a surface of a semiconductor substrate;

a device region on the surface of the semiconductor substrate between said isolation regions;

a gate electrode formed on said semiconductor substrate in said device region;

a channel region formed on a surface region of said semiconductor substrate under said gate electrode;

a plurality of source/drain electrodes formed on said semiconductor substrate surface, said channel being sandwiched therebetween; and

a carbon containing insulation layer formed under the source/drain electrodes.

2. A semiconductor device, as set forth in claim 1, wherein said source/drain electrodes contact said carbon containing insulation layer.

3. A semiconductor device, as set forth in claim 1, wherein said source/drain electrodes are self-aligned with said insulation layer.

4. A semiconductor device, as set forth in claim 1, wherein a top surface of a source/drain electrode is disposed above said channel region.

5. A semiconductor device, as set forth in claim 1, further comprising an offset region comprising insulation layers between a source/drain electrode and said gate electrode.

6. A semiconductor device, as set forth in claim 1, wherein the entire body of a source/drain electrode is formed of a metal-semiconductor compound.