Voltage controlled resistance modulation for single event upset immunity

• US 6,271,568 B1
• Filed: 12/29/1997
• Issued: 08/07/2001
• Est. Priority Date: 12/29/1997
• Status: Expired due to Term

• Current Assignee: Aeroflex Colorado Springs Incorporated (Cobham PLC)
• Original Assignee: UTMC Microelectronic Systems, Inc. (Cobham PLC)
• Inventors: Woodruff, Richard L., Lachman, Jonathan E.
• Primary Examiner(s): Abraham, Fetsum
• Application Number:
  US08/999,346
• Time in Patent Office: 1,317 Days
• Field of Search: 365/154-156, 365/190, 257/536, 257/537, 257/538, 257/379
• US Class Current: 257/379
• CPC Class Codes: G11C 11/4125 Cells incorporating circuit means for protecting against loss of information

Abstract

An SRAM cell includes six transistors and two variable resistors. A first pair of transistors form a first inverter, while a second pair of transistors form a second inverter. The remaining two transistors are pass transistors. The inverters are cross-coupled, through the variable resistors, to form a flip flop circuit which stores binary logic states. The variable resistors are formed by doping a portion of a polysilicon layer. Above the doped polysilicon resistor is a thin oxide layer. Disposed above the oxide layer is a thin layer of aluminum or polysilicon, which is connected by metallization. When a positive voltage is applied to the metallization, electrons accumulate in the doped polysilicon resistor, thereby lowering the resistance value of the polysilicon region. This voltage is applied to the interconnect during a write-in cycle, when it is desired to write data to the SRAM cell. The lowered resistance value of the polysilicon resistor allows for relatively fast write-in times for the SRAM cell. At all other times, no voltage is applied to the interconnect. As such, the resistance value of the doped resistor polysilicon region remains at a relatively high value, thereby providing for a high RC time delay and increased immunity to soft errors or single event upsets which may be caused by ionizing radiation.

Claims

1. Electrical circuitry, comprising:

first inverter means, having an input node and an output node, for storing any one of two different binary logic states;

second inverter means, having an input node and an output node, for storing an opposite one of the any one of the two binary logic states stored by the first inverter means;

first variable resistance means, connected between the output node of the first inverter means and the input node of the second inverter means, wherein the first variable resistance means comprises a first region of silicon doped with an impurity to form a predetermined resistivity, and the resistivity of the first variable resistance means can be varied by applying an electrical charge over the first region of silicon in accordance with a first voltage signal; and

second variable resistance means, connected between the output node of the second inverter means and the input node of the first inverter means, wherein the second variable resistance means comprises a second region of silicon doped with an impurity to form a predetermined resistivity, and the resistivity of the second variable resistance means can be varied by applying an electrical charge over the second region of silicon in accordance with a second voltage signal.

2. The electrical circuitry of claim 1, further comprising first transfer means connected to the output node of the first inverter means, wherein the first transfer means receives the first voltage signal for controlling transfer of a voltage signal output by the first inverter means.

3. The electrical circuitry of claim 1, further comprising second transfer means connected to the output node of the second inverter means, wherein the second transfer means receives first voltage signal for controlling transfer of a voltage signal output by the second inverter means.

4. The electrical circuitry of claim 1, wherein the first inverter means comprises a first transistor having a gate terminal, a source terminal and a drain terminal, and the first inverter means further comprises a second transistor having a gate terminal, a source terminal and a drain terminal, wherein the gate terminal of the first transistor is connected to the gate terminal of the second transistor, wherein the drain terminal of the first transistor is connected to the drain terminal of the second transistor, and wherein the source terminal of the first transistor is connected to a first voltage potential and the source terminal of the second transistor is connected to a second voltage potential, and wherein the drain terminal of the first transistor is connected to the drain terminal of the second transistor to form an output node of the first inverter means, wherein the output node of the first inverter means is connected to the first transfer means.

5. The electrical circuitry of claim 4, wherein the first and the second variable resistance means are formed in the same silicon layer as the gate terminals of the first transistor and the second transistor.

6. The electrical circuitry of claim 1, wherein the first variable resistance means comprises a region of silicon doped with an impurity comprising boron.

7. The electrical circuitry of claim 1, wherein the first variable resistance means comprises a region of silicon doped with an impurity comprising phosphorous.

8. The electrical circuitry of claim 1, wherein the second variable resistance means comprises a region of silicon doped with an impurity comprising boron.

9. The electrical circuitry of claim 1, wherein the second variable resistance means comprises a region of silicon doped with an impurity comprising phosphorous.

10. The electrical circuitry of claim 1, wherein the first voltage signal and the second voltage signal are the same.

11. The electrical circuitry of claim 1 further comprising an insulator layer located above the first variable resistance means and below an electrically conductive region.

12. The electrical circuitry of claim 11 wherein the insulator layer is a dielectric oxide.

13. A memory device, comprising:

a flip flop comprising first inverter means, having an input node and an output node, for storing any one of two different binary logic states, the flip flop further comprising second inverter means, having an input node and an output node, for storing an opposite one of the any one of the two binary logic states stored by the first inverter means; and

first variable resistance means, connected between the output node of the first inverter means and the input node of the second inverter means, wherein the first variable resistance means comprises a first region of silicon doped with an impurity to form a predetermined resistivity, and the resistivity of the first variable resistance means can be varied by applying an electrical charge over the first region of silicon in accordance with a first voltage signal.

14. The memory device of claim 13, further comprising:

second variable resistance means, connected between the output node of the second inverter means and the input node of the first inverter means, wherein the second variable resistance means comprises a second region of silicon doped with an impurity to form a predetermined resistivity, and the resistivity of the first variable resistance means can be varied by applying an electrical charge over the second region of silicon in accordance with a second voltage signal.

15. The memory device of claim 14, wherein the first variable resistance means comprises a region of polycrystalline silicon doped with an impurity comprising boron.

16. The memory device of claim 14, wherein the first variable resistance means comprises a region of silicon doped with an impurity comprising phosphorous.

17. The memory device of claim 14, wherein the second variable resistance means comprises a region of silicon doped with an impurity comprising boron.

18. The memory device of claim 14, wherein the second variable resistance means comprises a region of silicon doped with an impurity comprising phosphorous.

19. The electrical circuitry of claim 14, wherein the first voltage signal and the second voltage signal are the same.

20. The memory device of claim 14, further comprising first transfer means connected to the output node of the first inverter means, wherein the first transfer means receives the first voltage signal for controlling transfer of a voltage signal output by the first inverter means.

21. The memory device of claim 14, further comprising second transfer means connected to the output node of the second inverter means, wherein the second transfer means receives the first voltage signal for controlling transfer of a voltage signal output by the second inverter means.

22. The memory device of claim 14, wherein the first inverter means comprises a first transistor having a gate terminal, a source terminal and a drain terminal, and the first inverter means further comprises a second transistor having a gate terminal, a source terminal and a drain terminal, wherein the gate terminal of the first transistor is connected to the gate terminal of the second transistor, wherein the drain terminal of the first transistor is connected to the drain terminal of the second transistor, and wherein the source terminal of the first transistor is connected to a first voltage potential and the source terminal of the second transistor is connected to a second voltage potential, and wherein the drain terminal of the first transistor is connected to the drain terminal of the second transistor to form an output node of the first inverter means, wherein the output node of the first inverter means is connected to the first transfer means.

23. The electrical circuitry of claim 22, wherein the first and the second variable resistance means are formed in the same silicon layer as the gate terminals of the first transistor and the second transistor.

24. The electrical circuitry of claim 13 further comprising an insulator layer located above the first variable resistance means and below an electrically conductive region.

25. The electrical circuitry of claim 24 wherein the insulator layer is a dielectric oxide.

26. A variable resistor disposed between an output node of a first inverter and an input node of a second inverter on a semiconductor substrate, the variable resistor comprising:

a polysilicon layer over the semiconductor substrate, the polysilicon layer having a variable resistor region that is doped with an impurity to form a predetermined resistivity;

an electrically conductive region over the variable resistor region; and

,

a dielectric oxide layer between the polysilicon layer and the electrically conductive region,

wherein the resistivity of the variable resistor region can be adjusted by applying a voltage signal to the electrically conductive region.

27. The variable resistor of claim 26, wherein the electrically conductive region comprises polysilicon.

28. The variable resistor of claim 26, wherein the electrically conductive region comprises aluminum.

29. The variable resistor of claim 26, wherein the electrically conductive region has a thickness of about 500 to 5000 Angstroms.

30. The variable resistor of claim 26, wherein the electrically conductive region has a thickness of about 1000 Angstroms.

31. The variable resistor of claim 26, wherein the electrically conductive region has substantially the same width as the variable resistor region and is positioned over the variable resistor region.

32. The variable resistor of claim 26, wherein the impurity is implanted in the variable resistor region at a dose ranging from 1×

10¹³ to 1×

10¹⁶ atoms/cm³, and an energy level in the range of 15 keV to 60 keV.

33. The variable resistor of claim 26, wherein the impurity comprises phosphorous.

34. The variable resistor of claim 26, wherein the impurity comprises arsenic.

35. The variable resistor of claim 26 wherein the dielectric oxide layer comprises silicon dioxide.

36. A memory device comprising:

first and second inverters, each having an input node and an output node;

a first variable resistor connected between the output node of the first inverter and the input node of the second inverter, wherein the first variable resistor comprises a first region of silicon doped with an impurity to form a predetermined resistivity, and the resistivity of the first variable resistor can be varied by applying an electrical charge over the first region of silicon in accordance with a first voltage signal; and

a second variable resistor, connected between the output node of the second inverter and the input node of the first inverter, wherein the second variable resistor comprises a second region of silicon doped with an impurity to form a predetermined resistivity, and the resistivity of the second variable resistor can be varied by applying an electrical charge over the second region of silicon in accordance with a second voltage signal.

37. The electrical circuitry of claim 36 further comprising an insulator layer located above the first variable resistor and below an electrically conductive region.

38. The electrical circuitry of claim 37 wherein the insulator layer is a dielectric oxide.