I/O cell configuration for multiple I/O standards

• US 6,271,679 B1
• Filed: 03/23/2000
• Issued: 08/07/2001
• Est. Priority Date: 03/24/1999
• Status: Expired due to Term

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Cliff, Richard G., Wang, Bonnie I., McClintock, Cameron
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): LE, DON P
• Application Number:
  US09/535,064
• Time in Patent Office: 502 Days
• Field of Search: 326/37-41, 326/83, 326/86, 326/80, 326/81
• US Class Current: 326/38
• CPC Class Codes: H03K 19/018585 programmable
• CPC Class Codes: H03K 19/17744 for input/output signals

Abstract

Circuitry is provided to individually configure each I/O of an integrated circuit to be compatible with a different LVTTL I/O standards. This can be done with only one I/O supply voltage, where that voltage is the highest of the I/O voltages needed in a particular application. The circuitry operates by regulating the output voltage of the I/O cell so that it is above the VOH and below the maximum VIH for the LVTTL standard for which it will comply with. Since each I/O cell is individually configurable, any I/O can drive out to any LVTTL specification.

Claims

1. A programmable logic integrated circuit comprising:

a plurality of first I/O circuits coupled to a supply voltage and a first configurable reference voltage; and

a plurality of second I/O circuits coupled to the supply voltage and a second configurable reference voltage, wherein the first configurable reference voltage is different from the second configurable reference voltage and the plurality of first I/O circuits is compatible with a first I/O standard based on the first configurable reference voltage and the plurality of second I/O circuits compatible with a second I/O voltage standard based on the second configurable reference voltage.

2. The integrated circuit of claim 1 wherein each of the plurality of first I/O circuits comprises:

a first transistor coupled between the supply voltage and a first node, and having a control electrode coupled to a voltage level equal to the first reference voltage plus a threshold voltage of the first transistor;

a second transistor coupled between the first node and a pad; and

a third transistor coupled between the pad and ground.

3. The integrated circuit of claim 2 wherein the first transistor is NMOS and the second transistor in PMOS, and the first transistor is at least about ten times larger in size than the second transistor.

4. The integrated circuit of claim 2 wherein a VOH of the first I/O circuit is the lesser of the first reference voltage or the supply voltage.

5. The integrated circuit of claim 1 wherein each of the plurality of second I/O circuits comprises:

a first transistor coupled between the supply voltage and a pad;

a second transistor coupled between the pad and ground;

a logic gate having an output coupled to a control electrode of the first transistor; and

a differential amplifier circuit having a first input coupled to the pad and a second input coupled to the second reference voltage, and providing an output to an input of the logic gate, wherein the output is a logic high when a voltage at the second input is higher than a voltage at the first input, and the output is a logic low when the voltage at the first input is higher than the voltage at the second input.

6. The integrated circuit of claim 5 wherein a VOH of the second I/O circuit is the lesser of the second reference voltage or the supply voltage.

7. The integrated circuit of claim 5 wherein the second I/O circuit further comprises a leaker device coupled between the supply voltage and the pad to statically hold a VOH voltage at the pad.

8. The integrated circuit of claim 5 wherein the logic gate further comprises an input coupled to a predriver circuit.

9. The integrated circuit of claim 7 wherein the first transistor and leaker device are PMOS transistors and the first transistor is larger in size than the leaker device.

10. The integrated circuit of claim 1 wherein the first configurable reference voltage is programmably selectable by configuring memory cells of the integrated circuit.

11. The integrated circuit of claim 1 wherein the first and second I/O circuits each comprise:

a first multiplexer having a first input programmably coupled to an interconnect line and a second input coupled to a pad;

an output register having a input coupled to an output of the first multiplexer; and

a second multiplexer having a first input programmably coupled to the interconnect line and a second input coupled to an output of the output register, and providing an output to an input of the I/O circuit.

12. The integrated circuit of claim 1 wherein a VOH of the first I/O circuits will be the lesser of the first configurable reference voltage or the supply voltage, and a VOH of the second I/O circuits will be the lesser of the second configurable reference voltage or the supply voltage.

13. The integrated circuit of claim 1 wherein the supply voltage is a noisy supply and a second supply voltage at the same voltage level as the noisy supply voltage is a quiet supply voltage coupled to circuitry other than the I/O circuits of integrated circuit.

14. A method of operating a programmable logic integrated circuit comprising:

programmably selecting a first reference voltage level to be coupled to a first I/O circuit to select a first I/O standard the first I/O circuit will be compatible with;

programmably selecting a second reference voltage level to be coupled to a second I/O circuit to select a second I/O standard the second I/O circuit will be compatible with; and

coupling the first I/O circuit and the second I/O circuit to a supply voltage.

15. The method of claim 14 wherein the supply voltage is the highest supply voltage of the first or second I/O standard.