Dual port memory system for buffering asynchronous input to a raster scanned display

• US 6,271,866 B1
• Filed: 12/23/1998
• Issued: 08/07/2001
• Est. Priority Date: 12/23/1998
• Status: Expired due to Fees

• Current Assignee: Honeywell Incorporated (Honeywell International Inc.)
• Original Assignee: Honeywell International Inc.
• Inventors: Hancock, William Ray, Quirk, Robert John
• Primary Examiner(s): Chauhan, Ulka J.
• Application Number:
  US09/219,959
• Time in Patent Office: 958 Days
• Field of Search: 345/503, 345/531, 345/544, 345/547, 345/554, 345/565, 348/715, 348/718, 348/719
• US Class Current: 345/544
• CPC Class Codes: G09G 2340/0435 Change or adaptation of the frame rate of the video stream
• CPC Class Codes: G09G 5/12 Synchronisation between the display unit and other units, e.g. other display units, video-disc players
• CPC Class Codes: G09G 5/39 Control of the bit-mapped memory
• CPC Class Codes: G11C 8/16 Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups

Abstract

A system which utilizes dual-port memory to seamlessly display video frames on a raster scanned display device. Dual port memory is partitioned into a ‘single frame buffer’ having sufficient capacity to buffer a full video frame, and an ‘extension buffer’ which is a contiguous extension of the single frame buffer. The two sections together comprise an ‘extended buffer’. As long as the video memory write and read addresses are sufficiently separated by a predetermined number of lines, video data is written and read using the single frame buffer for each frame. When the write and read addresses are closer than a predetermined number of lines, the incoming video data for the next several new frames is written using the ‘extended’ buffer, and also read therefrom. After the write and read addresses are again sufficiently separated, video data is written and read using only the single frame buffer.

Claims

1. A method for controlling the reading from and writing to dual-port memory used as a buffer for storing digital video data to be displayed on a raster scanned display, wherein the video data is written to a write address in said memory and is read from a read address in said memory, and wherein the video data is received asynchronously with respect to the display rate of the raster scanned display, the method comprising the steps of:

partitioning said memory into an extended buffer including a single frame buffer capable of storing one frame of the video data, and an extension buffer for storing additional said video data, wherein said extension buffer is a contiguous extension of said single frame buffer;

determining a number of lines of separation in said memory between a present said read address and a present said write address;

writing the video data to said extended buffer, in response to a situation wherein said separation is not more than a predetermined number of said lines;

writing the video data to said single frame buffer, in response to a situation wherein said separation is more than said predetermined number of lines, and

reading the video data for a most recently completed written frame.

2. The method of claim 1, wherein said extension buffer has a capacity of at least one third of a said frame of video data.

3. The method of claim 1 wherein said predetermined number of lines is determined by multiplying a total number of said lines in said frame by the absolute value of a percentage difference between a video data receive rate and said display rate.

4. The method of claim 1, wherein:

when said wrap-around mode is set, said video data is written to memory addresses extending sequentially through said single frame buffer from a first end thereof, through said extension buffer, and wrapping back to said first end of said single frame buffer.

5. The method of claim 1, comprising the additional steps of:

initializing a wrap counter when said buffer wrap-around mode is set; and

incrementing said wrap counter each time a write sync signal is received;

wherein the step of terminating said buffer wrap-around mode is performed only after said wrap counter equals a predetermined maximum value.

6. The method of claim 5, wherein said predetermined maximum value is an integer having a value between 2 and 5, inclusive.

7. A method for controlling the reading from and writing to dual-port memory used as a buffer for storing digital video data to be displayed on a raster scanned display, the video data being written to a write address in said memory and being read from a read address in said memory, wherein the video data is received asynchronously with respect to the display rate of the raster scanned display, the method comprising the steps of:

(a) partitioning said memory into an extended buffer including a single frame buffer capable of storing one frame of the video data, and an extension buffer for storing additional said video data, wherein said extension buffer is a contiguous extension of said single frame buffer;

(b) receiving a write frame sync signal;

(c) determining a number of lines of separation in said memory between a present said read address and a present said write address;

(d) in response to a situation wherein said separation is not more than a predetermined number of said lines;

if buffer wrap-around mode is set,

writing the video data to said extended buffer; and

reading the video data from said extended buffer;

if said buffer wrap-around mode is not set,

setting said buffer wrap-around mode;

continuing to read the video data from said single frame buffer; and

writing the video data to said extended buffer space;

(e) in response to a situation wherein said separation is more than said predetermined number of lines;

if said buffer wrap-around mode is set,

terminating said buffer wrap-around mode; and

processing the video data by writing to and reading from said extended buffer;

if said buffer wrap-around mode is not set,

processing the video data by writing to and reading from said single frame buffer.

8. The method of claim 7, wherein said extension buffer has a capacity of at least one third of a said frame of video data.

9. The method of claim 7, wherein said predetermined number of lines is determined by multiplying a total number of said lines in said frame by the absolute value of a percentage difference between a video data receive rate and said display rate.

10. The method of claim 7, wherein:

when said wrap-around mode is set, said video data is written to memory addresses extending sequentially through said single frame buffer from a first end thereof, through said extension buffer, and wrapping back to said first end of said single frame buffer.

11. The method of claim 7, comprising the additional steps of:

initializing a wrap counter when said buffer wrap-around mode is set; and

incrementing said wrap counter each time a write sync signal is received;

wherein the step of terminating said buffer wrap-around mode is performed only after said wrap counter equals a predetermined maximum value.

12. The method of claim 11, wherein said predetermined maximum value is an integer having a value between 2 and 5, inclusive.

13. A system for managing video data to be displayed on a raster scanned video display device having dual-port memory connected thereto, wherein said data is written to a write address in said memory, and is read to said display device from a read address in said memory, wherein said memory includes a frame buffer for storing one frame of the video data, and an extension buffer, contiguous to said frame buffer, for storing additional said video data, the system comprising:

address compare logic for generating a minimum spacing signal when said write address is separated from said read address by a minimum spacing;

wrap counter logic for generating a wrap mode inhibit signal in response to simultaneously receiving said minimum spacing signal and a write sync signal, and for suppressing said wrap mode inhibit signal in absence of said minimum spacing signal, wherein said wrap mode inhibit signal is suppressed until a predetermined number of said write sync signals have been received;

gate logic for generating a counter reset signal in response to simultaneously receiving said minimum spacing signal, said wrap mode inhibit signal and said write sync signal;

a write address counter for incrementing said write address and for initializing said write address in response to said counter reset signal;

field delay logic for initializing said read address in response to simultaneously receiving said counter reset signal and a read sync signal, if said counter reset signal was received subsequent to the previous said write sync signal; and

a read address counter for incrementing said read address, and for initializing said read address in response to a signal from said field delay logic.

14. The system of claim 13, wherein said wrap counter logic causes said write address counter to initialize said write address when said write sync signal is detected, if said minimum spacing signal is detected and said wrap mode inhibit signal is being generated, otherwise said wrap counter logic allows said write address counter to continue incrementing from its present position.

15. The system of claim 13, wherein said raster scanned video display device is an LCD display.

16. A system for managing video data to be displayed on a raster scanned video display device having dual-port memory connected thereto, wherein said data is written to a write address in said memory, and is read to said display device from a read address in said memory, wherein said memory includes a frame buffer for storing one frame of the video data, and an extension buffer, contiguous to said frame buffer, for storing additional said video data, the system comprising:

address compare means for generating a minimum spacing signal when said write address is separated from said read address by a minimum spacing;

wrap counter means for generating a wrap mode inhibit signal in response to simultaneously receiving said minimum spacing signal and a write sync signal, and for suppressing said wrap mode inhibit signal in absence of said minimum spacing signal, wherein said wrap mode inhibit signal is suppressed until a predetermined number of said write sync signals have been received;

gate means for generating a counter reset signal in response to simultaneously receiving said minimum spacing signal, said wrap mode inhibit signal and said write sync signal;

a write address counter for incrementing said write address and for initializing said write address in response to said counter reset signal;

field delay means for initializing said read address in response to simultaneously receiving said counter reset signal and a read sync signal, if said counter reset signal was received subsequent to the previous said write sync signal; and

a read address counter for incrementing said read address, and for initializing said read address in response to a signal from said field delay means.

17. The system of claim 16, wherein said wrap counter means causes said write address counter to initialize said write address when said write frame signal is detected, if said minimum spacing signal is detected and said wrap mode inhibit signal is being generated, otherwise said wrap counter means allows said write address counter to continue incrementing from its present position.

18. The system of claim 16, wherein said predetermined number of said write sync signals is an integer between 2 and 5, inclusive.

19. The system of claim 16, wherein said minimum spacing is determined by multiplying a total number of said lines in said frame by the absolute value of a percentage difference between a rate at which said video data is received and a rate at which said video data is displayed on said display device.

20. The system of claim 16, wherein said predetermined number of said write sync signals is equal to 3.