Time division multiplexer-demultiplexer and method of operation thereof

• US 6,272,130 B1
• Filed: 01/19/1998
• Issued: 08/07/2001
• Est. Priority Date: 01/16/1997
• Status: Expired due to Term

• Current Assignee: Physical Optics Corporation
• Original Assignee: Physical Optics Corporation
• Inventors: Lin, Freddie, Jannson, Tomasz P., Panahi, Allen
• Primary Examiner(s): Hsu, Alpus H.
• Assistant Examiner(s): HO, DUC CHI
• Application Number:
  US09/008,849
• Time in Patent Office: 1,296 Days
• Field of Search: 370/366, 370/352, 370/353, 370/425, 370/426, 370/375, 370/522, 370/466, 370/535, 370/538, 370/464, 370/294
• US Class Current: 370/366
• CPC Class Codes: H04J 3/08 Intermediate station arrangements, e.g. for branching, for tapping-off
• CPC Class Codes: H04J 3/1605 Fixed allocated frame structures

Abstract

Systems and methods for time division multiplexing are described. A time division multiplexer-demultiplexer system includes I) a signal transmitting system for transmittal of a serialized signal including A) latency free continuous data and B) at least one member selected from the group consisting of bursty data and packetized data, the signal transmitting system including a multiplexer and a timing control block; and II) a signal receiving system for reception of the signal without disrupting the laminarity of the latency free continuous data, the signal receiving system including a demultiplexer and a sequence detector. The systems and methods provide advantages in that continuous data can be simultaneously transmitted with bursty data and/or packetized data on the same tie line without disrupting the laminarity of the continuous data.

Claims

1. An add/drop multiplexer, comprising:

(A) a signal transmitting system for simultaneous transmittal, on a first single tie line, of latency free continuous data and at least one member selected from the group consisting of bursty data and packetized data, said signal transmitting system including (1) a time division multiplexer, (2) an analog-to-digital convertor for simultaneous transmittal of base band latency free continuous real time audio and video data connected to said time division multiplexer, (3) a timing control block connected to said time division multiplexer, (4) a first FIFO memory buffer connected to both said time division multiplexer and said timing control block and (5) a clock multiplier connected to said multiplexer;

(B) a signal receiving system for simultaneous reception, on a second tie line, of latency free continuous data and at least one member selected from the group consisting of bursty data and packetized data, said signal receiving system including (1) a time division demultiplexer, (2) a digital-to-analog convertor for simultaneous reception of base band latency free continuous real time audio and video data connected to said time division demultiplexer, (3) a state machine connected to said demultiplexer, and (4) a second FIFO memory buffer connected to both said demultiplexer and said state machine;

(C) a switch for dropping and adding signals connected to both said multiplexer and said demultiplexer; and

(D) a network access port for simultaneous (1) full duplex messaging between a first user and a second user and (2) management of a network including dynamic reallocation of network resources, said network access port being connected to said switch for dropping and adding signals, wherein said network access port includes at least one subport selected from the group consisting of an RS232 subport with a full hand shake interface, an RS422 subport, an RS485 subport, a SCSI subport and a full duplex 10 Mb/sec packetized data subport.

2. A system, comprising:

(A) a signal transmitting system for transmitted of a serialized signal including (1) latency free non compressed continuous data and (2) at least one member selected from a group consisting of bursty data and packetized data, said signal transmitting system including a multiplexer and a timing control block; and

(B) a signal receiving system for reception of said signal without disrupting the laminarity of the latency free continuous data, said signal receiving system including a demultiplexer and a sequence detector;

(C) a network access port for simultaneous (1) full duplex messaging between a first user and a second user and (2) management of a network including dynamic reallocation of network resources, said network access port being connected to both said multiplexer and said demultiplexer,

wherein said network access port includes at least one subport selected from the group consisting of an RS232 subport with a full hand shake interface, an RS422 subport, an RS485 subport, a SCSI subport and a full duplex packetized data subport.

3. The apparatus of claim 2, wherein said multiplexer includes a time division multiplexer, said signal transmitting system includes an analog-to-digital convertor for simultaneous transmittal of base band latency free continuous real time audio and video data, said demultiplexer includes a time division demultiplexer and said signal receiving system includes a digital-to-analog convertor for simultaneous reception of base band latency free continuous real time audio and video data.

4. The apparatus of claim 3, further comprising a wavelength division multiplexer coupled to said time division multiplexer and a wavelength division demultiplexer coupled to said time division demultiplexer.

5. The apparatus of claim 2, further comprising a full duplex dedicated router interconnect connected to both said signal transmitting system and said signal receiving system, said full duplex dedicated router interconnect being selected from the group consisting of a single full duplex wave division multiplexer optical fiber and a pair of simplex optical fibers.

6. The apparatus of claim 2, wherein said network access port includes at least one subport selected from the group consisting of an RS232 subport with fill hand shake support, an RS422 subport, an RS485 subport, a SCSI subport and a full duplex 10 Mb/sec packetized data subport.

7. The apparatus of claim 2 wherein said network access port includes a subport for asynchronous data communication.

8. The apparatus of claim 2, further comprising a switch for dropping and adding signals connected to at least one of said multiplexer and said demultiplexer.

9. The apparatus of claim 2, further comprising a 2:

1 bypass switch for redundant switching, said 2;

1 bypass switch being coupled to said demultiplexer.

10. A method of communicating a serialized signal, comprising:

(A) providing a signal transmitting system and a signal receiving system, said transmitting system including a time division multiplexer, a timing control circuit, and a memory buffer, and said receiving system including a time division demultiplexer;

(B) receiving a first stream of data at said signal transmitting system from a first data source, and then providing said first stream of data to a first input channel of said time division multiplexer, said first stream of data comprising latency free continuous data;

(C) receiving a second stream of data at said signal transmitting system from a second data source, said second stream of data comprising at least one member selected from the group consisting of bursty data and packetized data, said receiving step including (1) providing said second stream of data to said memory buffer and (2) controlling the flow of said second stream of data through said memory buffer using said timing control circuit to modify timing characteristics of said second stream of data, and then providing said second stream of data to a second input channel of said time division multiplexer;

(D) time division multiplexing said first and second streams of data using said time division multiplexer to produce said serialized signal in the form of a third stream of data that is a time-multiplexed combination of said first and second streams of data;

(E) transmitting said third stream of data on a single tie line using said signal transmitting system;

(F) receiving said third stream of data from said single tie line using said signal receiving system; and

(G) time division demultiplexing said third stream of data using said time division demultiplexer to recover said first and second streams of data, said first and second streams of data being produced at first and second output channels of said time division demultiplexer.

11. The method of claim 10, wherein the step of providing includes providing a drop-add switch for dropping and adding signals, said drop-add switch being connected to both said time division multiplexer and said time division demultiplexer and, further comprising, reconfiguring said drop-add switch using data from said signal.

12. The method of claim 10, wherein said memory buffer comprises a first-in-first-out memory buffer.

13. The method of claim 12, wherein said first-in-first-out memory buffer is approximately eight bits deep.

14. The method of claim 10, wherein said first stream of data is an uncompressed stream of data, said uncompressed stream of data comprising at least one member selected from the group consisting of real time video data and real time audio data, and said uncompressed data stream being produced by sampling said first data source, said first data source being an analog signal source.

15. The method of claim 10, wherein said time division multiplexing step is performed entirely at a physical layer of said transmitting system and said time division demultiplexing step is performed entirely at a physical layer of said receiving system.

16. The method of claim 10,

wherein said memory buffer is a first memory buffer and said timing control circuit is a first timing control circuit, and

wherein the method further comprises the following steps, which are performed after said time division demultiplexing step

providing said second stream of data to a second memory buffer, and

controlling the flow of said second stream of data through said second memory buffer using a second timing control circuit.

17. The method of claim 16, wherein said first and second memory buffers respectively comprise first and second first-in-first-out memory buffers.

18. The method of claim 16, wherein said second timing control circuit comprises a state machine.

19. The method of claim 10, further comprising receiving a fourth stream of data at said transmitting system, said fourth stream of data comprising at least one member selected from the group consisting of wide area network data and asynchronous transfer mode data, and wherein said third data stream is also a time division multiplexed combination of said fourth data stream.

20. A communication system comprising:

(A) a tie line;

(B) a signal transmitting system, including

(1) a time division multiplexer, including

(a) a first multiplexer input channel, said first multiplexer input channel receiving a first stream of data, said first stream of data comprising latency free continuous data and being received from a first data source,

(b) a second multiplexer input channel, said second multiplexer input channel receiving a second stream of data, said second stream of data comprising at least one member selected from a group consisting of bursty data and packetized data, and said second stream of data being received from a second data source,

(c) a multiplexer output channel, said multiplexer output channel being coupled to said tie line and transmitting a third stream of data over said tie line, said third stream of data being a time division multiplexed combination of said fist and second streams of data,

(2) a timing control circuit, and

(3) a memory buffer, said memory buffer being interconnected between said second multiplexer input channel and said second data source, and said memory buffer being controlled by said timing control circuit to store bits of data from said second steam of data for variable periods of time as said second stream of data passes through said memory buffer; and

(C) a signal receiving system, including a time division demultiplexer including

(1) a demultiplexer input channel, said demultiplexer input channel being coupled to said multiplexer output channel by way of said tie line,

(2) a first demultiplexer output channel, said first demultiplexer output channel outputting said fist stream of data, and

(3) a second demultiplexer output channel, said second demultiplexer output channel outputting said second stream of data.

21. The communication system of claim 20, wherein said memory buffer comprises a first-in-first-out memory buffer.

22. The communication system of claim 21, wherein said first-in-first-out memory buffer is approximately eight bits deep.

23. The communication system of claim 20, wherein said first stream of data is an uncompressed stream of data, said uncompressed stream of data being at least one member selected from the group consisting of real time video data and real time audio data, and said uncompressed data stream being produced by sampling said first data source, said first data source being an analog signal source.

24. The communication system of claim 20,

wherein said memory buffer is a first memory buffer and said timing control circuit is a first timing control circuit, and

wherein said receiving system further includes

a second timing control circuit, and

a second memory buffer, said memory buffer being coupled to said second demultiplexer output channel and receiving said second stream of data, and said memory buffer being controlled by said second timing control circuit.

25. The method of claim 24, wherein said first and second memory buffers respectively comprise first and second first-in-first-out memory buffers.

26. The method of claim 24, wherein said second timing control circuit comprises a state machine.

27. The communication system of claim 20, wherein said transmitting system includes an analog-to-digital convertor that is interconnected between said first data source and said first multiplexer input channel, and wherein said demultiplexer includes digital-to-analog convertor that is connected to said first demultiplexer output channel.

28. Apparatus, comprising:

(A) a signal transmitting system for transmittal of a serialized signal including (1) latency free continuous data and (2) at least one member selected from the group consisting of bursty data and packetized data, said signal transmitting system including (1) a multiplexer, (2) a timing control block connected to said multiplexer, (3) a first FIFO memory buffer having an almost empty flag, said first FIFO being connected to both said multiplexer and said timing control block, (4) a clock multiplier connected to said multiplexer and (5) an analog-to-digital convertor connected to said multiplexer; and

(B) a signal receiving system for reception of said signal without disrupting the laminarity of the latency free continuous data, said signal receiving system including (1) a demultiplexer (2) a state machine connected to said demultiplexer, (3) a second FIFO memory buffer connected to both said demultiplexer and said state machine and (4) a digital-to-analog convertor connected to said demultiplexer.

29. An apparatus comprising:

(A) a signal transmitting system for transmittal of a serialized signal including (1) latency free non-compressed continuous data and (2) at least one member selected from a group consisting of bursty data and packetized data, said signal transmitting system including a multiplexer and a timing control block; and

(B) a signal receiving system for reception of a signal without disrupting the laminarity of the latency free continuous data, said signal receiving system including a demultiplexer and a sequence detector;

(C) a switch for dropping and adding signals connected to at least one of said multiplexer and said demultiplexer; and

(D) a network access port for simultaneous (1) full duplex messaging between a first user and a second user and (2) management of a network including dynamic reallocation of network resources, said network access port being connected to said switch for dropping and adding signals,

wherein said network access port includes at least one subport selected from the group consisting of an RS232 subport with a full hand shake interface, an RS422 subport, an RS485 subport, a SCSI subport and a fill duplex packetized data subport.

30. The apparatus of claim 29 wherein said network access port includes a subport for asynchronous data communication.