Receiver to recover data encoded in a serial communication channel

• US 6,272,193 B1
• Filed: 09/27/1999
• Issued: 08/07/2001
• Est. Priority Date: 09/27/1999
• Status: Expired due to Fees

• Current Assignee: Hanger Solutions, LLC (IP Investments Group LLC)
• Original Assignee: Genesis Microchip Inc. (STMicroelectronics NV)
• Inventors: Eglit, Alexander Julian
• Primary Examiner(s): Ghebretinsae, Temesghen
• Application Number:
  US09/406,332
• Time in Patent Office: 680 Days
• Field of Search: 375/355, 375/324, 375/354, 375/316, 370/503, 329/304
• US Class Current: 375/355
• CPC Class Codes: G09G 5/008 Clock recovery
• CPC Class Codes: H04L 7/0338 the correction of the phase error being performed by a feed forward loop

Abstract

A receiver to recover data encoded at high speed in a signal over a serial communication channel. A static phase determination circuit indicates whether the signal is early, late or neutral relative to a sampling clock. The sampling clock is used to oversample the signal to generate multiple samples. A token analyzer examines the transitions around a current symbol to determine any short term phase shifts of the boundaries between symbols. The short term phase shifts and the static phase together may be used to accurately select the samples representing the symbols without requiring extensive processing.

Claims

1. A method of recovering a plurality of symbols transmitted over a serial communication channel in the form of a signal, said method comprising:

(a) receiving said signal;

(b) over sampling said signal to generate a plurality of samples corresponding to each of said plurality of symbols;

(c) generating a sampling clock signal, wherein said sampling clock signal controls said over sampling of (b);

(d) generating a plurality of transition indicators, wherein each transition indicator indicates the presence of a transition in value between two successive samples;

(e) determining a static phase status representing a long term phase shift of said signal relative to said sampling clock signal, wherein said long term phase shift of said signal is determined based on many prior samples corresponding to a plurality of prior symbols;

(f) examining a plurality of transition indicators corresponding to a few symbols including a current symbol to determine any short term phase shift of boundaries between symbols around said current symbol; and

(g) selecting a sample corresponding to said current symbol according to said static phase status and said short term phase shift,

wherein the selection based on said short term phase shift enables the sample corresponding to said current symbol to be selected accurately, and

wherein the selection based on said static phase status enables th processing to be minimized in said selection.

2. The method of claim 1, wherein steps (e) and (g) are performed in parallel.

3. The method of claim 2, wherein said plurality of symbols are encoded with an alphabet containing two elements.

4. The method of claim 2, wherein step (d) comprises generating an XOR of two consecutive samples.

5. The method of claim 1, wherein (f) comprises:

(h) examining transitions corresponding to only said current symbol, and wherein said sample corresponding to said current symbol is selected according to the transitions corresponding to said current symbol and said static phase status.

6. The method of claim 5, and wherein said method further comprises:

(i) dividing said plurality of transition indicators into a plurality of tokens, with each token containing a number of transition indicators equal to said factor.

7. The method of claim 6, wherein each token is associated with a symbol, and wherein the token corresponding to said current symbol is determined by said sampling clock signal.

8. The method of claim 7, further comprising

(j) examining the tokens corresponding to said few symbols to determine any shift in boundaries relative to said sampling clock signal, wherein the determination as to shift in boundaries is used in computing said static phase status.

9. The method of claim 8, wherein said static phase status indicates whether said signal is early, late or neutral relative to the determination of said sampling clock signal.

10. The method of claim 9, further comprising:

(k) generating hard identifiers when the examination of (j) indicates that said signal is early, late or neutral relative to said sampling clock signal; and

(l) generating soft identifiers when the indication examination of (j) indicates that said signal is not early, not late or not neutral.

11. The method of claim 10, wherein said hard identifiers are given more weight than said soft identifiers in determining said static phase status.

12. The method of claim 1, wherein said signal is oversampled by a factor of 3.

13. The method of claim 1, wherein said method is implemented in a display unit to recover pixel data elements encoded in a display signal.

14. A circuit to recover a plurality of symbols encoded in a signal on a serial communication channel, said circuit comprising:

a clock generator to generate a sampling clock signal;

an analog to digital converter (ADC) to oversample said signal to generate a plurality of samples corresponding to each of said plurality of symbols, wherein said ADC over samples under the control of said sampling clock signal;

a transition detector to generate a plurality of transition indicators, wherein each transition indicator indicates the presence of a transition in value between two successive samples;

a static phase determination circuit to determine a static phase status representing a long term phase shift of said signal relative to said sampling clock signal, wherein said long term phase shift of said signal is determined based on many prior samples corresponding to a plurality of prior symbols; and

a tokens analyzer to examine a plurality of transition indicators corresponding to a few symbols including a current symbol to determine any short term phase shift of boundaries between symbols around said current symbol, said token analyzer to determine which sample represents said current symbol according to said long term phase shift and said short term phase shift; and

a samples selector to select said sample determined by said token analyzer as representing said current symbol,

wherein the selection based on said term phase shift enables the sample representing said current symbol to be selected accurately, and

wherein the selection based on said static phase status enables the processing to be minimized in said selection.

15. The circuit of claim 14, wherein said plurality of symbols are encoded with an alphabet containing two elements, and wherein said transition detector comprises a plurality of XOR gates to generate an XOR of two successive samples.

16. The circuit of claim 15, further comprises:

a token assembler for dividing said plurality of transition indicators into a plurality of tokens, with each token containing a number of transition indicators equal to a oversampling factor, wherein each token is associated with a symbol, and wherein the token corresponding to said current symbol is determined by said sampling clock signal.

17. The circuit of claim 16, wherein said tokens analyzer and said static phase determination circuit are designed to examine the tokens corresponding to said few symbols to determine any shift in boundaries relative to said sampling clock signal, wherein the determination as to shift in boundaries is used in computing said static phase status.

18. The circuit of claim 17, wherein said static phase determination circuit indicates whether said signal is early, late or neutral relative to the determination of said sampling clock signal.

19. The circuit of claim 18, wherein said static phase determination circuit is designed to generate hard identifiers if the examination of tokens corresponding to said few symbols indicates that said signal is early, late or neutral relative to said sampling clock signal, and to generate soft identifiers if the examination of tokens corresponding to said few symbols indicates that said signal is not early, not late or not neutral.

20. The circuit of claim 19, wherein said hard identifiers are given more weight than said soft identifiers in determining said static phase status.

21. The circuit of claim 14, wherein said signal is oversampled by a factor of 3.

22. The circuit of claim 21, wherein said tokens analyzer is designed to examine transition indicators corresponding to only said current symbol, and wherein said sample corresponding to said current symbol is selected according to the transitions corresponding to said current symbol and said static phase status.

23. The circuit of claim 14, wherein said static phase determination circuit and said samples selector are designed to operate in parallel.

24. A circuit to recover a plurality of symbols encoded in a signal on a serial communication channel, said circuit comprising:

receiving means for receiving said signal;

over sampling means for over sampling said signal to generate a plurality of samples corresponding to each of said plurality of symbols;

first generating means for generating a sampling clock signal, wherein said sampling clock signal controls said over sampling means;

second generating means for generating a plurality of transition indicators, wherein each transition indicator indicates the presence of a transition in value between two successive samples;

determination means for determining a static phase status representing a long term phase shift of said signal relative to said sampling clock signal, wherein said long term phase shift of said signal is determined based on many prior samples corresponding to a plurality of prior symbols;

examination means for examining a plurality of transition indicators corresponding to a few symbols including a current symbol to determine any short term phase shift of boundaries between symbols around said current symbol; and

selection means for selecting a sample from the samples corresponding to said current symbol according to said status and said short term phase shift,

wherein the selection based on said term phase shift enables the sample corresponding to said current symbol to be selected accurately, and

wherein the selection based on said phase status enables the processing to be minimized in said selection.

25. The circuit of claim 24, wherein said plurality of symbols are encoded with an alphabet containing two elements, and wherein said transition detector comprises a plurality of XOR gates to generate an XOR of two successive samples.

26. The circuit of claim 25, further comprises:

a token assembler means for dividing said plurality of transition indicators into a plurality of tokens, with each token containing a number of transition indicators equal to a oversampling factor, wherein each token is associated with a symbol, and wherein the token corresponding to said current symbol is determined by said sampling clock signal.

27. The circuit of claim 26, wherein said examination means and said determination means are designed to examine the tokens corresponding to said few symbols to determine any shift in boundaries relative to said sampling clock signal, wherein the determination as to shift in boundaries is used in computing said static phase status.

28. The circuit of claim 27, wherein said determination means indicates whether said signal is early, late or neutral relative to the determination of said sampling clock signal.

29. The circuit of claim 28, wherein said determination means is designed to generate hard identifiers if the examination of tokens corresponding to said few symbols indicates that said signal is early, late or neutral relative to said sampling clock signal, and to generate soft identifiers if the examination of tokens corresponding to said few symbols indicates that said signal is not early, not late or not neutral.

30. The circuit of claim 29, wherein said hard identifiers are given more weight than said soft identifiers in determining said static phase status.

31. The circuit of claim 24, wherein said signal is oversampled by a factor of 3.

32. The circuit of claim 24, wherein said examination means is designed to examine transition indicators corresponding to only said current symbol, and wherein said sample corresponding to said symbol is selected according to the transitions corresponding to said symbol and said phase status.

33. The circuit of claim 24, wherein said determination means and said selection means are designed to operate in parallel.