Monolithic PC audio circuit

• US 6,272,465 B1
• Filed: 09/22/1997
• Issued: 08/07/2001
• Est. Priority Date: 11/02/1994
• Status: Expired due to Term

• Current Assignee: Intellectual Ventures I LLC (Intellectual Ventures LLC)
• Original Assignee: Legerity Incorporated (Microsemi Semiconductor Corp.)
• Inventors: Brehmer, Geoffrey E., Blumenthal, Jeffrey M., Guercio, David, Cabler, Carlin Dru, Torok, Alan T., Feemster, Ryan, Spak, Michael E., Hogan, Michael, Hewitt, Larry D., Gulick, Dale E., Norris, David, Suggs, David N., Soques, Martin P., Linz, Alfredo R., Brown, Glen W., Schnizlein, Paul G.
• Primary Examiner(s): Hudspeth, David R.
• Assistant Examiner(s): MCFADDEN, SUSAN IRIS
• Application Number:
  US08/934,969
• Time in Patent Office: 1,415 Days
• Field of Search: 704/258, 704/500, 704/501, 704/502, 704/503, 704/201, 704/205
• US Class Current: 704/258
• CPC Class Codes: G06F 3/162 Interface to dedicated audio devices, e.g. audio drivers, interface to CODECs
• CPC Class Codes: G06F 7/026 Magnitude comparison, i.e. determining the relative order of operands based on their numerical value, e.g. window comparator
• CPC Class Codes: G06F 9/3869 Implementation aspects, e.g. pipeline latches; pipeline synchronisation and clocking
• CPC Class Codes: G10H 1/0066 using a MIDI interface
• CPC Class Codes: G10H 1/125 using a digital filter
• CPC Class Codes: G10H 2220/315 for joystick-like proportional control of musical input; Videogame input devices used for musical input or control, e.g. gamepad, joysticks joysticks per se G06F3/033, G05G9/047, A63F13/20
• CPC Class Codes: G10H 2230/035 Power management, i.e. specific power supply solutions for electrophonic musical instruments, e.g. auto power shut-off, energy saving designs, power conditioning, connector design, avoiding inconvenient wiring
• CPC Class Codes: G10H 2240/311 MIDI transmission G10H2240/056 takes precedence
• CPC Class Codes: G10H 2250/191 Chebyshev polynomials, e.g. to provide filter coefficients for sharp rolloff filters Chebyshev filters G10H2250/091; Chebyshev windows G10H2250/271
• CPC Class Codes: G10H 2250/545 Aliasing, i.e. preventing, eliminating or deliberately using aliasing noise, distortions or artifacts in sampled or synthesised waveforms, e.g. by band limiting, oversampling or undersampling, respectively
• CPC Class Codes: G10H 2250/571 Waveform compression, adapted for music synthesisers, sound banks or wavetables audio compression G10L19/00
• CPC Class Codes: G10H 2250/605 Dynamic range companding algorithms, e.g. "mu"-law, primarily used in the digital telephone systems of North America and Japan, or A-law as used in European digital telephone systems
• CPC Class Codes: G10H 2250/611 Waveform decimation, i.e. integer division of the sampling rate for reducing the number of samples in a discrete-time signal, e.g. by low-pass anti-alias filtering followed by the actual downsampling
• CPC Class Codes: G10H 7/002 using a common processing for different operations or calculations, and a set of microinstructions (programme) to control the sequence thereof
• CPC Class Codes: G10H 7/02 in which amplitudes at successive sample points of a tone waveform are stored in one or more memories
• CPC Class Codes: H03K 23/68 with a base which is a non-integer

Abstract

A monolithic integrated circuit for providing enhanced audio performance in personal computers. The monolithic circuit includes a wavetable synthesizer; a full function stereo coding and decoding circuit including analog-to-digital and digital-to-analog conversion; data compression, and mixing and muxing of analog signals; a local memory control module for interfacing with external memory; a game-MIDI port module; a system bus interface; and a control module for compatibility and circuit control functions.

Claims

1. A monolithic audio processing integrated circuit for a host computer system, said host computer system including a central processor, system memory and a processor-accessible bus for transferring data, control and address signals within said host computer system, said monolithic audio processing integrated circuit comprising:

a system control module which includes;

an interface to a bus accessible by said host processor; and

a plurality of integrated circuit control registers for storing data, control and status bits which reflect or control the status of various operations performed by said integrated circuit;

a coding and decoding module for providing analog-to-digital and digital-to-analog signal conversion;

said coding and decoding module further comprising;

analog input and analog output circuits having input and output terminals for receiving and transmitting, respectively, analog signals from and to external sources and destinations; and

digital audio input and digital audio output circuits having input and output terminals for receiving and transmitting, respectively, digital audio data from and to said system control module, and from and to external sources and destinations; and

a digital wavetable audio synthesizer module for generating digital audio signals, said synthesizer module further comprising;

a digital signal transfer circuit for transferring synthesized digital audio data to said coding and decoding module; and

a data input circuit for acquiring digital audio data from an external source.

2. The monolithic audio processing integrated circuit of claim 1, wherein said synthesizer module further comprises a memory circuit for storing digital audio data.

3. The monolithic audio processing integrated circuit of claim 1, wherein said system control module further comprises a register data bus for distributing data throughout said integrated circuit, said register data bus being in communication with each of said modules.

4. The monolithic audio processing integrated circuit of claim 3, wherein said register data bus further comprises an external bus interface circuit to couple said register data bus to said processor-accessible bus.

5. The monolithic audio processing integrated circuit of claim 3, wherein said data register bus includes two 8-bit or 16-bit input/output accesses between said integrated circuit and said host system.

6. The monolithic audio processing integrated circuit of claim 1, wherein said system control module further comprises an interrupt circuit for generating and managing processor interrupt signals in response to circuit requirements.

7. The monolithic audio processing integrated circuit of claim 1, wherein said system control module further comprises a direct memory access circuit for generating and managing direct memory access request and acknowledge signals in response to circuit requirements.

8. The monolithic audio processing integrated circuit of claim 1, wherein said system control module further comprises an internal clock circuit for receiving an external oscillator input signal and for providing an audio processing clock signal.

9. The monolithic audio processing integrated circuit of claim 8, wherein said internal clock circuit further comprises a clock stabilization circuit which includes means for disabling said audio processing clock signal during periods when said external oscillator signal is degraded.

10. The monolithic audio processing integrated circuit of claim 9, wherein said clock stabilization circuit comprises:

an oscillator stabilization circuit for detecting the condition of said external oscillator signal and for generating a clock signal representative of the state of said external oscillator signal; and

a clock control circuit adapted to respond to said clock control signal to enable or to disable said audio processing clock signal.

11. The monolithic audio processing integrated circuit of claim 1, wherein said synthesizer module further comprises a digital signal transfer circuit for transferring synthesized digital audio data to said coding and decoding module.

12. The monolithic audio processing integrated circuit of claim 1, wherein said synthesizer module comprises:

means for generating digital audio data for a plurality of voices;

means for combining said digital audio data for said voices into a composite digital audio signal;

a plurality of programmable synthesizer voice control registers; and

means for varying the frequency of each voice in response to the state of said programmable registers.

13. The monolithic audio processing integrated circuit of claim 1, wherein said synthesizer module further comprises a data input circuit for acquiring audio signal data from an external source.

14. The monolithic audio processing integrated circuit of claim 1, further comprising:

a game port module which includes;

an analog input circuit for receiving game control signals from external devices; and

an analog-to-digital conversion circuit for converting analog input signals to digital signals.

15. The monolithic audio processing integrated circuit of claim 1, further comprising a musical instrument digital interface (MIDI) module for facilitation data communication between said integrated circuit and external devices.

16. The monolithic audio processing integrated circuit of claim 1, wherein said system control module includes a memory access mode control register and a mode control signal generation circuit for generating one or more memory mode control signals, and wherein said state machine includes logic circuitry for generating delay states to provide for expanded time periods in which to communicate with said external memory device.

17. The monolithic audio processing integrated circuit of claim 1, further comprising a register controlled power-down signal generation circuit to conserve energy usage.

18. The monolithic audio processing integrated circuit of claim 1, wherein said analog input and output terminals are segregated from said digital audio input and output terminals.

19. The monolithic audio processing integrated circuit of claim 1, wherein a system power input terminal and a system ground input terminal are provided for said analog circuit.

20. The monolithic audio processing integrated circuit of claim 1, wherein said internal clock circuit comprises a digital clock generation circuit for providing a first timing signal for digital circuit operations performed by said integrated circuit and an analog clock generation circuit for providing a second timing signal for analog circuit operations performed by said integrated circuit, wherein said second timing signal is independent of said first timing signal.

21. The monolithic audio processing integrated circuit of claim 1, wherein said integrated circuit includes a plurality of addressable registers, and wherein said system control module includes means for enabling direct accesses to said registers by an external control device.

22. The monolithic audio processing integrated circuit of claim 1, wherein said system control module includes a buffering circuit for buffering input and output signals communicated between said integrated circuit and said processor-accessible bus.

23. The monolithic audio processing integrated circuit of claim 22, wherein said buffering circuit includes means for delaying subsequent input/output operations between said integrated circuit and said processor-accessible bus until prior buffered input/output operations have been completed.

24. The monolithic audio processing integrated circuit of claim 1, further comprising a local memory control module for coupling said integrated circuit with an external memory device.

25. The monolithic audio processing integrated circuit of claim 24, wherein said local memory control module includes a memory interface circuit for generating address and control signals for enabling data transfers between said integrated circuit and said external memory device.

26. The monolithic audio processing integrated circuit of claim 25, wherein said memory interface circuit includes means for interfacing with external random access memory (RAM) devices and read only memory (ROM) devices.

27. The monolithic audio processing integrated circuit of claim 25, wherein said memory interface circuit further comprises a serial data communication circuit for receiving serial audio data from an external memory device, and logic circuitry for generating control signals for communicating with said external memory device.

28. The monolithic audio processing integrated circuit of claim 25, wherein said memory interface circuit includes a refresh circuit for generating refresh signals for external dynamic random access memory ((DRAM) devices.

29. The monolithic audio processing integrated circuit of claim 28, wherein said refresh circuit includes a logic circuit responsive to said power-down signal to provide refresh signals at a reduced rate.

30. The monolithic audio processing integrated circuit of claim 25, wherein said memory interface circuit includes:

address definition registers for defining the beginning address and the end address a block of memory included in an external memory device; and

an automatic address generation circuit to generate sequential address signals from the beginning to the end of said defined memory block.

31. The monolithic audio processing integrated circuit of claim 25, wherein said memory interface circuit includes means for enabling 8-bit or 16-bit accesses an external memory device.

32. The monolithic audio processing integrated circuit of claim 25, wherein said memory interface circuit includes means for generatmg address and control signals to define first-in/first-out (FIFO) registers said external memory device.

33. The monolithic audio processing integrated circuit of claim 24, wherein said local memory control module includes logic circuitry for defining independent memory cycles or RAM or ROM accesses, and includes a control circuit for multiplexing address, control and data communication between said integrated circuit and said external memory device over a common signal path.

34. The monolithic audio processing integrated circuit of claim 24, wherein said local memory control module further comprises a state machine for defining and controlling time periods in which selected modules of said integrated circuit may communicate with said external memory device.

35. The monolithic audio processing integrated circuit of claim 24, wherein said local memory control module includes:

an interrupt circuit for generating interrupt request signals for said host system processor;

means for receiving data from said host system memory; and

means for transferring said received data to said external memory device.

36. The monolithic audio processing integrated circuit of claim 24, wherein said local memory control module includes:

direct memory access (DMA) means for generating DMA request signals for said host system processor;

means for receiving data from said host system memory under DMA control; and

means for transferring the data received from said host system memory to said external memory device.

37. The monolithic audio processing integrated circuit of claim 36, wherein said DMA means includes means for interleaving data received from said host system memory while said received data is being stored in said external memory device.