Programmable and expandable fuzzy processor for pattern recognition

• US 6,272,476 B1
• Filed: 04/14/1999
• Issued: 08/07/2001
• Est. Priority Date: 04/14/1999
• Status: Active Grant

• Current Assignee: Winbond Electronics Corporation
• Original Assignee: Winbond Electronics Corporation
• Inventors: Shi, Bingxue, Lin, Gu
• Primary Examiner(s): Powell, Mark R.
• Assistant Examiner(s): BOOKER, KELVIN
• Application Number:
  US09/292,124
• Time in Patent Office: 846 Days
• Field of Search: 706/1, 706/4, 706/5, 382/224, 382/181
• US Class Current: 706/1
• CPC Class Codes: G06N 7/043 Analogue or partially analogue implementation
• CPC Class Codes: G06V 10/75 Organisation of the matching processes, e.g. simultaneous or sequential comparisons of image or video features; Coarse-fine approaches, e.g. multi-scale approaches; using context analysis; Selection of dictionaries
• CPC Class Codes: G06V 10/94 Hardware or software architectures specially adapted for image or video understanding

Abstract

A fuzzy processor which can be programmed and expanded is disclosed. The fuzzy processor has a membership function I/O circuit for inputting and outputting a plurality of membership functions respectively corresponding to each one of a plurality of features of each one of a plurality of standard patterns. A feature decoder receives a to-be-recognized pattern having a plurality of input features for generating a plurality of feature values. A membership function generator stores the plurality of membership functions and receives the plurality of feature values to generate a plurality of current-type membership degrees for the plurality of input features corresponding to the plurality of standard patterns respectively. A plurality of accumulators receive the plurality of current-type membership degrees respectively for generating a plurality of synthesis membership degrees. An expandable synthesis membership degree comparing circuit is provided for receiving the plurality of synthesis membership degrees from the plurality of accumulators to output said plurality of synthesis membership degrees as well as the corresponding standard patterns in an order of magnitude.

Claims

1. A fuzzy processor for operating with a plurality of standard patterns each having a plurality of features, said fuzzy processor comprising:

a membership function I/O circuit for inputting and outputting a plurality of membership functions respectively corresponding to each one of said plurality of features of each one of said plurality of standard patterns;

a feature decoder for receiving a to-be-recognized pattern having a plurality of input features, and generating a plurality of feature values;

a membership function generator for storing said plurality of membership functions and receiving said plurality of feature values to generate a plurality of current-type membership degrees for said plurality of input features corresponding to said plurality of standard patterns, respectively;

a plurality of accumulators for receiving said plurality of current-type membership degrees respectively and generating a plurality of synthesis membership degrees; and

an expandable synthesis membership degree comparing circuit for receiving said plurality of synthesis membership degrees from said plurality of accumulators and outputting said plurality of synthesis membership degrees as well as the corresponding standard patterns in an order of magnitude.

2. The fuzzy processor as claimed in claim 1, wherein said membership function generator comprises:

a plurality of membership function memory units respectively corresponding to each one of said plurality of features of each one said plurality of standard patterns respectively for storing said plurality of membership functions and addressed by said plurality of feature values to generate a plurality of membership degrees for said plurality of input features corresponding to said plurality of standard patterns, respectively; and

a plurality of current-type digital/analog converters corresponding to said plurality of standard patterns respectively for receiving said plurality of membership degrees and generating a plurality of current-type membership degrees.

3. The fuzzy processor as claimed in claim 2, wherein said membership function I/O circuit is enabled by activating a chip select signal to write said plurality of membership functions into said plurality of membership function memory units respectively.

4. The fuzzy processor as claimed in claim 3, wherein each one of said plurality of membership function memory units includes a plurality of static random access memory units.

5. The fuzzy processor as claimed in claim 4, wherein each one of said plurality of accumulators includes a plurality of storage units constructed by a Regulated-Gate Cascade structure.

6. The fuzzy processor as claimed in claim 5, wherein said expandable synthesis membership degree comparing circuit comprises:

an input circuit unit having a plurality of inputs for receiving a plurality of currents representing said plurality of synthesis membership degrees and having a plurality of outputs for outputting at least one of said plurality of currents;

a winner-take-all (WTA) circuit unit receiving said plurality of currents from said input circuit for establishing a plurality of representing voltages corresponding thereto wherein the maximum one among said plurality of representing voltages generates a representing current controlled by a control terminal to be output on a VO terminal, and generating a plurality of first voltage output signals respectively corresponding to the received plurality of currents for indicating said maximum current; and

a feedback control and voltage output unit having a clock terminal for receiving a clock signal, receiving said plurality of first voltage output signals from said winner-take-all circuit unit, generating a plurality of feedback control signals according to said plurality of first voltage output signals in one operation cycle controlled by said clock signal to control the outputs of said input circuit unit wherein one of said plurality of feedback control signals corresponding to the first voltage output signal indicative said maximum current is set inactive for guiding said input circuit unit to clear a corresponding input current, and converting said plurality of first voltage output signals to a plurality of second voltage output signals on said plurality of outputs in said operation cycle;

a reset terminal being provided for receiving reset signals to reset said feedback control and voltage output unit.

7. A fuzzy processor for operating with a plurality of standard patterns each having a plurality of features, said fuzzy processor comprising:

a membership function I/O circuit for inputting and outputting a plurality of membership functions respectively corresponding to each one of said plurality of features of each one of said plurality of standard patterns;

a feature decoder for receiving a to-be-recognized pattern having a plurality of input features, and generating a plurality of feature values;

a plurality of membership function memory units respectively corresponding to each one of said plurality of features of each one of said plurality of standard patterns for storing said plurality of membership functions and addressed by said plurality of feature values to generate a plurality of membership degrees for said plurality of input features corresponding to said plurality of standard patterns, respectively;

a plurality of current-type digital/analog converters corresponding to said plurality of standard patterns respectively for receiving said plurality of membership degrees and generating a plurality of current-type membership degrees;

a plurality of accumulators corresponding to said plurality of converters for receiving said plurality of current-type membership degrees and generating a plurality of synthesis membership degrees; and

an expandable synthesis membership degree comparing circuit including;

an input circuit unit having a plurality of inputs for receiving a plurality of currents representing said plurality of synthesis membership degrees and having a plurality of outputs for outputting at least one of said plurality of currents;

a winner-take-all (WTA) circuit unit receiving said plurality of currents from said input circuit for establishing a plurality of representing voltages corresponding thereto wherein the maximum one among said plurality of representing voltages generates a representing current controlled by a control terminal to be output on a VO terminal, and generating a plurality of first voltage output signals respectively corresponding to the received plurality of currents for indicating said maximum current; and

a feedback control and voltage output unit having a clock terminal for receiving a clock signal, receiving said plurality of first voltage output signals from said winner-take-all circuit unit, generating a plurality of feedback control signals according to said plurality of first voltage output signals in one operation cycle controlled by said clock signal to control the outputs of said input circuit unit wherein one of said plurality of feedback control signals corresponding to the first voltage output signal indicative said maximum current is set inactive for guiding said input circuit unit to clear a corresponding input current, and converting said plurality of first voltage output signals to a plurality of second voltage output signals on said plurality of outputs in said operation cycle;

a reset terminal being provided for receiving reset signals to reset said feedback control and voltage output unit.

8. The fuzzy processor as claimed in claim 7, wherein said membership function I/O circuit is enabled by activating a chip select signal to write said plurality of membership functions into said plurality of membership function memory units respectively.

9. The fuzzy processor as claimed in claim 8, wherein each one of said plurality of membership function memory units includes a plurality of static random access memory units.

10. The fuzzy processor as claimed in claim 9, wherein each one of said plurality of accumulators includes a plurality of storage units constructed by a Regulated-Gate Cascade structure.

11. An expanded fuzzy processor comprising a plurality of fuzzy processors as claimed in claim 7, wherein said reset terminals, said clock terminals and said VO terminals of said plurality of fuzzy processors are connected together respectively and wherein one of said control terminal of said fuzzy processor is set active and the others are set inactive.