System for interposing a multi-port internally cached DRAM in a control path for temporarily storing multicast start of packet data until such can be passed

• US 6,272,567 B1
• Filed: 11/24/1998
• Issued: 08/07/2001
• Est. Priority Date: 11/24/1998
• Status: Expired due to Term

• Current Assignee: RPX Corporation
• Original Assignee: Nexabit Networks, Inc. (Nokia Corporation)
• Inventors: Ray, Rajib, Pal, Subhasis, Opalka, Zbigniew
• Primary Examiner(s): Lee, Thomas
• Assistant Examiner(s): ELAMIN, ABDELMONIEM I
• Application Number:
  US09/200,377
• Time in Patent Office: 987 Days
• Field of Search: 710/56, 710/2, 711/105, 711/119
• US Class Current: 710/56
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1075 for multiport memories each having random access ports and serial ports, e.g. video RAM
• CPC Class Codes: G11C 8/16 Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups

Abstract

A new data packet cell control method and apparatus, particularly, though not exclusively, for use with I/O packet cell source and destination resource networks using shared central multi-port internally cached dynamic random access memory (AMPIC DRAM), wherein a separate control path architecture is used, also incorporating AMPIC DRAM technology, to obviate problems with data traffic congestion resulting from significant I/O resource and for bandwidth requirement increases, and doing so while enabling scaling with data path, and retaining quality of service and increased multicast functionality, as well.

Claims

1. In a network for interfacing parallel I/O data packet information packets (PIP) source resources with I/O destination resources through a central shared memory data path comprised of a central shared multi-port internally cached DRAM memory system (AMPIC DRAM) and a separate control path therefor, and wherein each I/O resource has the capability simultaneously to receive PIP data stream traffic from all the other I/O resources, a method of eliminating PIP traffic congestion as the number of I/O resources and/or bandwidth requirements significantly increase, that comprises, interposing an AMPIC DRAM system in the control path for simultaneously absorbing and storing all PIP streams without stalling an I/O source resource incoming data stream, wherein the control path is provided for unicast traffic, and the interposed AMPIC DRAM system is separated into an AMPIC Quality of Service (QOS) memory for enabling priority control, and an AMPIC LINK memory for enabling packet re-assembly at I/O destination resources.

2. The method claimed in claim 1 wherein the AMPIC QOS and AMPIC LINK memories are respectively fed start of packet (SOP) control information, and continuation of packet (COP) and end of packet (EOP) information derived from the incoming PIP stream.

3. The method as claimed in claim 2 wherein the memory in the control path is provided with a number of available PIP buffers that is equal to the number of data buffers provided in the AMPIC DRAM central memory, thereby enabling the control path to absorb enormous bursts of PIP streams without stalling an I/O resource data stream.

4. The method as claimed in claim 2 wherein the control path is also provided with a multicast data traffic control path, and in which a further AMPIC DRAM memory is interposed for temporarily storing multicast SOP PIP data.

5. The method as claimed in claim 4 wherein the multicast SOP PIPs are exploded and interleaved fairly with the unicast path SOP PIPs, and then written into QOS fifo queues.

6. The method as claimed in claim 1 wherein each I/O resource operates with AMPIC DRAM used and free buffer address list for the shared AMPIC DRAM memory, and in the event that PIPs are returned to a source I/O resource because QOS queues are filled, and in order to avoid PIP return congestion, storing the returned PIP information in the AMPIC DRAMs and, when the last PIP is returned, clearing from the AMPIC used address memory and transferring to the AMPIC free address memory.

7. The method as claimed in claim 6 wherein there are N I/O resources requiring N bit masks for keeping track of used addresses, with the AMPIC used address memory reading N masks simultaneously in said time, updating the used and free address lists and keeping up with the maximum return PIP rate, enabling the PIP return path to remain uncongested and to scale with the forward PIP path and the shared memory datapath.

8. Apparatus for use in a network for interfacing parallel I/O data packet information packets (PIP) source resources with I/O destination resources through a central shared memory data path comprised of a central shared multi-port internally cached DRAM memory system (AMPIC DRAM) and a separate control path therefor, and wherein each I/O resource has the capability simultaneously to receive PIP data stream traffic from all other I/O resources, said apparatus having an architecture for eliminating PIP traffic congestion as the number of I/O resources and/or bandwidth requirements significantly increase, that comprises an AMPIC DRAM system interposed in the separate control path for simultaneously absorbing and storing all PIP streams without stalling any I/O source resource incoming data stream, wherein the control path is provided for unicast traffic, and the interposed AMPIC DRAM system is separated into an AMPIC Quality Of Service (QOS) memory for enabling priority control, and an AMPIC LINK memory for enabling packet reassembly at I/O destination resources.

9. Apparatus as claimed in claim 8 wherein the AMPIC QOS and AMPIC LINK memories are respectively fed start of packet (SOP) control information, and continuation of packet (COP) and end of packet (EOP) information derived from the incoming PIP stream.

10. Apparatus as claimed in claim 9 wherein the central shared memory AMPIC DRAM utilizes independent serial interfaces and data buffers arbitratively switch-connected under a dynamic configuration.

11. Apparatus as claimed in claim 10 wherein the memory in the separate control path is provided with a number of available PIP buffers that is equal to the number of data buffers provided in the AMPIC DRAM central memory, thereby enabling the control path to absorb enormous bursts of PIP streams without stalling any I/O resource data stream.

12. Apparatus as claimed in claim 9 wherein the control path is also provided with a multicast data traffic control path, and in which a further AMPIC DRAM memory is interposed therein for temporarily storing multicast SOP PIP data.

13. Apparatus as claimed in claim 12 wherein means is provided whereby the multicast SOP PIPs are exploded and interleaved fairly with the unicast path SOP PIPs, and then written into QOS fifo queues.

14. Apparatus as claimed in claim 9 wherein the SOP PIP information for writing into the AMPIC QOS memory is derived form the I/O source resource PIP streams through PIP processor staging fifos, with such memory being partitioned into QOS fifos, and with processor fifo pointers supplying addresses based on the QOS priority field stored in the SOS PIP.

15. Apparatus as claimed in claim 14 wherein the SOP PIP contains the relevant information for scheduling a data packet or cell, including channel and interface number, packet byte count and QOS priority, in a PIP scheduler comprising buffer read addresses for the central memory.

16. Apparatus as claimed in claim 9 wherein the COP/EOP PIP information for writing into the AMPIC COP/EOP LINK memory is derived from the I/O source resource PIP streams through PIP processor staging fifos, with such memory storing the link address embedded in the PIP for supplying the next buffer addresses in the packet or cell.

17. Apparatus as claimed in claim 16 wherein the splitting of the SOP and COP/EOP PIPs in the unicast path serves to maintain output bandwidth and predictable latency through the control path, with all COP/EOP PIPs being written to the LINK memory, and with no interaction with the QOS memory.

18. Apparatus as claimed in claim 17 wherein means is provided whereby the COP/EOP PIPs are stored with the corresponding SOP PIPs in the QOS fifo memory, and with the COP/EOP PIPs that are destined for the same queue from the I/O resource, ending up interleaved in the fifo.

19. Apparatus as claimed in claim 18 wherein the PIP sequencer is provided with means for dequeueing the SOP PIPs from the QOS memory using the embedded byte count and bandwidth requirements for different priority queues to calculate the next time to send a packet, and all associated COP PIPs then follow at line rate.

20. Apparatus as claimed in claim 19 wherein the PIP sequencer is provided with means for dequeueing the remainder of the packet by stripping the link address from the SOP PIP and injecting it into the AMPIC LINK memory table.

21. Apparatus as claimed in claim 20 wherein means is provided for enabling a scheduler to dequeue the COP/EOP PIPs at said line rate or faster, in order to prevent read address starvation which could result in the filling up of said central shared memory.

22. Apparatus as claimed in claim 9 wherein the AMPIC QOS memory is partitioned into priority queues with external fifo read and write pointers.

23. Apparatus as claimed in claim 22 wherein internal contention for a particular DRAM bank is obviated by internal wide-bus access to the embedded DRAM banks and by the provision of I/O slots for temporarily storing buffer data until the corresponding DRAM bank can read or write the data.

24. Apparatus as claimed in claim 12 wherein means is provided for diverting incoming multicast SOP PIPs from the AMPIC QOS memory, the multicast index being stripped from the SOP PIP and injected into a read port on said further AMPIC DRAM memory which serves as the AMPIC multicast memory.

25. Apparatus as claimed in claim 24 wherein, in the event of a multicast traffic explosion, means is provided for creating a new SOP PIP by replacing the destination address, QOS priority and other fields in the original SOP PIP, but without changing the original buffer address of the data packet or cell, and means for multiplexing the new SOP PIP back into the data path for the AMPIC QOS memory under arbiter control with the same treatment as the unicast traffic.

26. Apparatus as claimed in claim 25 wherein means is provided for replicating the new SOP PIP multiplexing the same N times, simultaneously to explode N multicast SOP PIPs from N I/O resource PIP streams.

27. Apparatus as claimed in claim 25 wherein the multiplexing means comprises an N×

N crossbar switch between the multicast data path and the unicast data path of the control path, enabling exploded multicast traffic to utilize idle write ports to the AMPIC QOS memory to drain the exploded multicast SOP PIPs into the QOS memory.

28. Apparatus as claimed in claim 25 wherein means is provided for requiring incoming multicast SOP PIPs to be stored in part of the AMPIC multicast memory until they can be processed, with such memory being organized into fifos provided with external logic for keeping track of read and write pointers thereof, thereby insuring that multicast SOP PIPs can be retrieved in the same order they came in so that no unfairness in queuing priorities is introduced.

29. Apparatus as claimed in claim 28 wherein the fifo memory storage is accessed by AMPIC multicast memory write ports, the multicast explosion only utilizing read ports thereof, and with the write ports absorbing multicast SOP PIP at the maximum PIP traffic rate.

30. Apparatus as claimed in claim 8 wherein each I/O resource is provided with used and free buffer address lists for the shared AMPIC DRAM memory.

31. Apparatus as claimed in claim 30 wherein, to accommodate the event that PIPs are returned to a source I/O resource because QOS queues are filled, and in order to avoid PIP return congestion, the used and free buffers each comprise AMPIC DRAMs for storing returned PIP information and, when the last PIP is returned, for clearing from the AMPIC used address memory and transferring to the AMPIC free address memory.

32. Apparatus for use in a network for interfacing parallel I/O data packet information packet (PIP) source resources with I/O destination resources through a central shared multi-port internally cached DRAM memory system (AMPIC DRAM) and a separate control path therefor, and wherein each I/O resource has the capability simultaneously to receive PIP data stream traffic from all the other I/O resources, said apparatus having a control path architecture for eliminating multicast data path traffic congestion, that comprises, interposing an AMPIC DRAM multicast memory in the control path for temporarily storing multicast start of packet (SOP) PIP data until such can be processed, wherein the multicast memory is organized into fifos provided with external logic for keeping track of read and write pointers thereof, thereby insuring that multicast SOP PIPs can be retrieved in the same order they came in so that no unfairness in queuing priorities is introduced.