System for interposing a multi-port internally cached DRAM in a control path for temporarily storing multicast start of packet data until such can be passed
First Claim
1. In a network for interfacing parallel I/O data packet information packets (PIP) source resources with I/O destination resources through a central shared memory data path comprised of a central shared multi-port internally cached DRAM memory system (AMPIC DRAM) and a separate control path therefor, and wherein each I/O resource has the capability simultaneously to receive PIP data stream traffic from all the other I/O resources, a method of eliminating PIP traffic congestion as the number of I/O resources and/or bandwidth requirements significantly increase, that comprises, interposing an AMPIC DRAM system in the control path for simultaneously absorbing and storing all PIP streams without stalling an I/O source resource incoming data stream, wherein the control path is provided for unicast traffic, and the interposed AMPIC DRAM system is separated into an AMPIC Quality of Service (QOS) memory for enabling priority control, and an AMPIC LINK memory for enabling packet re-assembly at I/O destination resources.
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Accused Products
Abstract
A new data packet cell control method and apparatus, particularly, though not exclusively, for use with I/O packet cell source and destination resource networks using shared central multi-port internally cached dynamic random access memory (AMPIC DRAM), wherein a separate control path architecture is used, also incorporating AMPIC DRAM technology, to obviate problems with data traffic congestion resulting from significant I/O resource and for bandwidth requirement increases, and doing so while enabling scaling with data path, and retaining quality of service and increased multicast functionality, as well.
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Citations
32 Claims
- 1. In a network for interfacing parallel I/O data packet information packets (PIP) source resources with I/O destination resources through a central shared memory data path comprised of a central shared multi-port internally cached DRAM memory system (AMPIC DRAM) and a separate control path therefor, and wherein each I/O resource has the capability simultaneously to receive PIP data stream traffic from all the other I/O resources, a method of eliminating PIP traffic congestion as the number of I/O resources and/or bandwidth requirements significantly increase, that comprises, interposing an AMPIC DRAM system in the control path for simultaneously absorbing and storing all PIP streams without stalling an I/O source resource incoming data stream, wherein the control path is provided for unicast traffic, and the interposed AMPIC DRAM system is separated into an AMPIC Quality of Service (QOS) memory for enabling priority control, and an AMPIC LINK memory for enabling packet re-assembly at I/O destination resources.
- 8. Apparatus for use in a network for interfacing parallel I/O data packet information packets (PIP) source resources with I/O destination resources through a central shared memory data path comprised of a central shared multi-port internally cached DRAM memory system (AMPIC DRAM) and a separate control path therefor, and wherein each I/O resource has the capability simultaneously to receive PIP data stream traffic from all other I/O resources, said apparatus having an architecture for eliminating PIP traffic congestion as the number of I/O resources and/or bandwidth requirements significantly increase, that comprises an AMPIC DRAM system interposed in the separate control path for simultaneously absorbing and storing all PIP streams without stalling any I/O source resource incoming data stream, wherein the control path is provided for unicast traffic, and the interposed AMPIC DRAM system is separated into an AMPIC Quality Of Service (QOS) memory for enabling priority control, and an AMPIC LINK memory for enabling packet reassembly at I/O destination resources.
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32. Apparatus for use in a network for interfacing parallel I/O data packet information packet (PIP) source resources with I/O destination resources through a central shared multi-port internally cached DRAM memory system (AMPIC DRAM) and a separate control path therefor, and wherein each I/O resource has the capability simultaneously to receive PIP data stream traffic from all the other I/O resources, said apparatus having a control path architecture for eliminating multicast data path traffic congestion, that comprises, interposing an AMPIC DRAM multicast memory in the control path for temporarily storing multicast start of packet (SOP) PIP data until such can be processed, wherein the multicast memory is organized into fifos provided with external logic for keeping track of read and write pointers thereof, thereby insuring that multicast SOP PIPs can be retrieved in the same order they came in so that no unfairness in queuing priorities is introduced.
Specification