Microprocessor architecture capable of supporting multiple heterogeneous processors

• US 6,272,579 B1
• Filed: 02/22/1999
• Issued: 08/07/2001
• Est. Priority Date: 07/08/1991
• Status: Expired due to Fees

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Seiko Epson Corporation (Seiko Group)
• Inventors: Nguyen, Le Trong, Lau, Te-Li, Lentz, Derek J., Hagiwara, Yasuaki, Tang, Cheng-Long
• Primary Examiner(s): Dinh, Dung C.
• Application Number:
  US09/253,761
• Time in Patent Office: 897 Days
• Field of Search: 710/116, 710/244, 710/41, 711/151, 711/158, 712/29
• US Class Current: 710/116
• CPC Class Codes: G06F 12/0215 with look ahead addressing means
• CPC Class Codes: G06F 12/0813 with a network or matrix configuration
• CPC Class Codes: G06F 12/0831 using a bus scheme, e.g. with bus monitoring or watching means
• CPC Class Codes: G06F 12/0855 Overlapped cache accessing, e.g. pipeline G06F12/0846 takes precedence
• CPC Class Codes: G06F 13/18 based on priority control G06F13/1605 takes precedence
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 15/167 using a common memory, e.g. mailbox
• CPC Class Codes: G06F 15/17 using an input/output type connection, e.g. channel, I/O port
• CPC Class Codes: G06F 15/173 using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake

Abstract

A system and method for transferring data in a multiprocessor architecture capable of supporting multiple processors. The system comprises a priority assignor that provides a dynamic priority to input/output unit (IOU), D-cache and I-cache devices requests as a function of an intrinsic priority assigned to each device and a plurality of factors including the existence of a row match between a requested address and a previously serviced request, the number of times a device has been denied service and the number of times a device has been serviced without interruption. The system also includes a tracker to keep track of the number of times each of the factors occurs and a priority changer to change the priority of the devices as a function of the intrinsic priority and the number.

Claims

1. A system for transferring data in a multiprocessor architecture capable of supporting multiple processors comprising:

a priority assignor that provides a dynamic priority to input/output unit (IOU), D-cache and I-cache devices requests as a function of an intrinsic priority assigned to each device and a plurality of factors including the existence of a row match between a requested address and a previously serviced request, the number of times a device has been denied service and the number of times a device has been serviced without interruption;

a tracker to keep track of the number of times each of said factors occurs; and

a priority changer to change the priority of said devices as a function of said intrinsic priority and said number.

2. The system of claim 1, further comprising:

an initializer to initialize a counter with a predetermined count when a device is, first serviced after an interruption;

a decrementer to decrement said counter each time said device is serviced without interruption; and

a determiner to determine that said number of times a device has been serviced without interruption factor occurs for said device when said counter reaches zero.

3. The system of claim 1, further comprising:

an initializer to initialize a counter with a predetermined count when a device is first denied service after an interruption;

a decrementer to decrement said counter each time said device is denied service without interruption; and

a determiner to determine that said number of times a device has been denied service without interruption factor occurs for said device when said counter reaches zero.

4. A method of transferring data in a multiprocessor architecture capable of supporting multiple processors comprising the steps of:

providing a dynamic priority to input/output unit (IOU), D-cache and I-cache device requests as a function of an intrinsic priority assigned to each device and a plurality of factors including the existence of a row match between a requested address and a previously serviced request, the number of times a device has been denied service and the number of times a device has been serviced without interruption;

keeping track of the number of times each of said factors occurs; and

changing the priority of said devices as a function of said intrinsic priority and said number.

5. The method of claim 4, further comprising the steps of:

initializing a counter with a predetermined count when a device is first serviced after an interruption;

decrementing said counter each time said device is serviced without interruption; and

determining that said number of times a device has been serviced without interruption factor occurs for said device when said counter reaches zero.

6. The method of claim 4, further comprising the steps of:

initializing a counter with a predetermined count when a device is first denied service after an interruption;

decrementing said counter each time said device is denied service without interruption; and

determining that said number of times a device has been denied service without interruption factor occurs for said device when said counter reaches zero.

7. In a computer system having a memory array unit (MAU), a plurality of memory ports to provide access to said MAU, and a plurality of devices which access said MAU via said memory ports, a system for arbitrating for said memory ports, comprising:

a priority assignor to assign priorities to the devices, comprising

an initial priority assignor to assign an initial priority to each of said devices,

a first priority increaser to increase a priority associated with a first device having an initial priority less than a first priority value if said first device is repeatedly denied service to a memory port,

a priority decreaser to decrease a priority associated with a second device having an initial priority greater than a second priority value if it is determined that said second device is repeatedly granted service to a memory port, and

a second priority increaser to increase a priority associated with a third device if a row addressed by a pending memory access request issued by said third device matches a row addressed by a preceding memory access request last serviced by said MAU; and

a request servicer to service requests for the memory ports issued by the devices in accordance with said priorities.

8. In a computer system having a memory array unit (MAU), a plurality of memory ports to provide access to said MAU, and a plurality of devices which access said MAU via said memory ports, a method for arbitrating for said memory ports, comprising the steps of:

(1) assigning priorities to said devices; and

(2) servicing requests for said memory ports issued by said devices in accordance with said priorities;

wherein step (1) comprises the steps of;

(a) assigning an initial priority to each of said devices;

(b) increasing a priority associated with a first device having an initial priority less than a first priority value if said first device is repeatedly denied service to a memory port;

(c) decreasing a priority associated with a second device having an initial priority greater than a second priority value if it is determined that said second device is repeatedly granted service to a memory port; and

(d) increasing a priority associated with a third device if a row addressed by a pending memory access request issued by said third device matches a row addressed by a preceding memory access request last serviced by said MAU.