Method and apparatus for transfer of data between cache and flash memory in an internal combustion engine control system

• US 6,272,587 B1
• Filed: 05/12/1999
• Issued: 08/07/2001
• Est. Priority Date: 09/30/1996
• Status: Expired due to Term

• Current Assignee: Cummins Incorporated
• Original Assignee: Cummins Incorporated
• Inventors: Irons, John M.
• Primary Examiner(s): PEIKARI, BEHZAD
• Application Number:
  US09/310,283
• Time in Patent Office: 818 Days
• Field of Search: 711/103, 711/118, 711/1, 711/3, 711/143, 711/162, 365/185.03, 365/229, 713/502, 714/6
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0638 Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module address formation of the next microinstruction G06F9/26; masking faults in memories by using spares or by reconfiguring G11C29/70
• CPC Class Codes: G06F 12/08 in hierarchically structured memory systems, e.g. virtual memory systems
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G06F 2212/251 Local memory within processor subsystem
• CPC Class Codes: G06F 2212/253 Centralized memory

Abstract

In a microprocessor-based automotive control system including flash memory and a RAM cache sized substantially smaller than the storage capacity of the flash memory, a caching technique is operable, in accordance with one aspect of the invention, to move areas of the flash memory into and out of the cache. The flash memory is updated by the contents of the cache each time the a new access is attempted to an area of flash memory or after a predefined time period has elapsed since such an access has been attempted. In accordance with another aspect of the invention, 9 bit storage within the flash memory is disallowed and only word (16 bit) or longword (32 bit) storage is allowed therein, so that the flash memory is addressable only on even boundaries thereof. A software algorithm is operable to modify a request for access to an odd flash memory address so that the request properly points to an address of the cache that contains the actual data of interest.

Claims

1. A method of accessing flash memory in an internal combustion engine control system, said method comprising the steps of:

providing an auxiliary memory cache having substantially faster access speed than the flash memory and substantially smaller data storage capacity than the flash memory;

copying data stored in a first area of the flash memory into said auxiliary memory cache;

operating on any of said copied data in said auxiliary memory cache; and

writing said operated on data in said auxiliary memory cache back into said first area of the flash memory, in response to either of two conditions;

(a) the passage of a predetermined time period of approximately twenty-four hours since the copying step, or (b) an attempted read or write access to an area of the flash memory containing flash memory data not presently contained within said auxiliary memory cache, whichever occurs first.

2. The method of claim 1 wherein the data storage capacity of said auxiliary memory cache is equal to the amount of data stored in said first area of the flash memory.

3. The method of claim 1 wherein said first area of the flash memory includes a number of data entries each having a flash memory address associated therewith.

4. The method of claim 3 wherein said auxiliary memory cache includes a corresponding number of data entries after completion of the copying step, each of said cache data entries having a cache address and corresponding flash memory address associated therewith.

5. An automotive electronic control system comprising:

a flash memory unit;

a cache having substantially smaller data storage capacity than said flash memory unit; and

a processor having means for copying data stored in a first area of said flash memory unit into said cache and means for writing data in said cache back into said first area of said flash memory unit, in response to either of two conditions;

(a) the passage of a predetermined time period of approximately twenty-four hours since the copying step, or (b) an attempted read from or write to an area of the flash memory unit containing flash memory data not currently contained within said cache, whichever occurs first.

6. The system of claim 5 wherein the data storage capacity of said cache is equal to the amount of data stored in said first area of said flash memory unit.

7. The system of claim 5 wherein said first area of said flash memory unit includes a number of data entries each having a flash memory address associated therewith.

8. The system of claim 7 wherein said cache includes a number of data entries identical to said number of data entries in said flash memory unit, each of said number of data entries in said cache having a cache address and corresponding flash memory address associated therewith.