Method and apparatus for verifying and characterizing data retention time in a DRAM using built-in test circuitry
First Claim
1. A method for verifying a data retention time in a dynamic random access memory (DRAM) using built-in test circuitry, comprising the steps of:
- providing a DRAM having a plurality of rows of memory cells, each row periodically requiring a refresh operation to retain valid data;
providing refresh control circuitry coupled to the DRAM, the refresh control circuitry providing at least one signal to the DRAM which initiates the refresh operation of the DRAM, the DRAM requiring every row to periodically receive a refresh operation to satisfy a data retention time specification for the DRAM; and
providing built-in test circuitry coupled to the refresh control circuitry and the DRAM, the built-in test circuitry dynamically determines a limit for reliable data retention of the DRAM by testing the DRAM with application of variable refresh rates until at least a first failure of data retention is encountered and scaling a rate of memory refresh at which the DRAM is being refreshed, the scaling being between a normal rate at which the refresh control circuitry initiates a refresh operation and a rate equal to the product of;
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Abstract
A BIST controller (112) and methodology uses the DRAM controller (108) refresh signals to test the data retention characteristics of a DRAM memory array (132). The BIST controller blocks a fraction of the refresh cycles generated by the DRAM controller to provide a margin of confidence above the DRAM'"'"'s specified retention time. The BIST controller is especially suited to embedded applications in which access to the memory is indirect and to applications in which the memory system is modular. The invention may also be used to characterize the actual retention time of a particular DRAM allowing the system to optimize the DRAM'"'"'s refresh interval.
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Citations
11 Claims
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1. A method for verifying a data retention time in a dynamic random access memory (DRAM) using built-in test circuitry, comprising the steps of:
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providing a DRAM having a plurality of rows of memory cells, each row periodically requiring a refresh operation to retain valid data;
providing refresh control circuitry coupled to the DRAM, the refresh control circuitry providing at least one signal to the DRAM which initiates the refresh operation of the DRAM, the DRAM requiring every row to periodically receive a refresh operation to satisfy a data retention time specification for the DRAM; and
providing built-in test circuitry coupled to the refresh control circuitry and the DRAM, the built-in test circuitry dynamically determines a limit for reliable data retention of the DRAM by testing the DRAM with application of variable refresh rates until at least a first failure of data retention is encountered and scaling a rate of memory refresh at which the DRAM is being refreshed, the scaling being between a normal rate at which the refresh control circuitry initiates a refresh operation and a rate equal to the product of;
- View Dependent Claims (2, 3, 4, 5, 6)
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7. A memory with data retention test capability, comprising:
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a dynamic random access memory (DRAM) array having rows and columns of memory cells, each one of the rows being specified to be refreshed within a predetermined refresh period;
a DRAM controller coupled to the DRAM, the DRAM controller providing refresh signals to the DRAM to control timing of refreshing of data of each one of the rows of the DRAM; and
test circuitry coupled to the DRAM, the test circuitry modifying the timing of refreshing of data by the DRAM controller with circuitry which selectively nullifies every N out of (M+N) DRAM refresh operations, where N is less than M, and N and M are integers, and thereby scales the DRAM refresh relative to the predetermined refresh period. - View Dependent Claims (8)
a programmable counter coupled to the DRAM, the programmable counter counting values for N and M, where N is provided by a user of the memory.
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9. A memory test circuit for testing data retention of a DRAM, comprising:
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test circuitry which electrically monitors data refresh signals provided to the DRAM, the test circuitry selectively nullifying every N out of (M+N) data refresh signals, where N is less than M, and N and M are integers, the test circuitry verifying a data retention time characteristic of the DRAM, the test circuitry being clocked by a clock signal having a frequency which does not affect or modify a test interval period for testing the data retention of the DRAM. - View Dependent Claims (10, 11)
a programmable circuit for permitting a user to program a value for N.
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11. The memory test circuit of claim 9 wherein the test circuitry further comprises:
a characterization circuit which provides a plurality of values of N from zero to (M−
1), thereby permitting the memory test circuit to characterize limits of reliable data retention of the DRAM.
Specification