Method and apparatus for executing multiple instruction streams in a digital processor with multiple data paths
First Claim
Patent Images
1. An integrated circuit having a single digital processor for switching between different modes of operation, said single digital processor comprising:
- a first instruction pipeline comprising a first fetch stage, a first decoder stage, and a first execute stage, for processing data responsive to an instruction stream;
a second instruction pipeline comprising a second fetch stage, a second decoder stage, and a second execute stage, for processing data responsive to an instruction stream; and
a controller, responsive to a first instruction in an instruction stream being processed in said first instruction pipeline, for activating at least a portion of said second instruction pipeline in a first mode in which said second decoder stage and said second execute stage operate upon instructions retrieved by said first fetch stage while said first decoder stage and said first execute stage also operate upon said instructions retrieved by said first fetch stage, wherein said second fetch stage is deactivated when said single digital processor is in said first mode.
10 Assignments
0 Petitions
Accused Products
Abstract
A parallel processing architecture for a digital processor capable of alternately operating in a single threaded mode, a SIMD (single instruction, multiple data) mode and a MIMD (multiple instructions, multiple data) mode. The instruction set for the processor includes instructions for switching between modes and exchanging data between the parallel processing paths. The hardware in any instruction path or portion of an instruction path which is not being used is deactivated to save power.
-
Citations
48 Claims
-
1. An integrated circuit having a single digital processor for switching between different modes of operation, said single digital processor comprising:
-
a first instruction pipeline comprising a first fetch stage, a first decoder stage, and a first execute stage, for processing data responsive to an instruction stream;
a second instruction pipeline comprising a second fetch stage, a second decoder stage, and a second execute stage, for processing data responsive to an instruction stream; and
a controller, responsive to a first instruction in an instruction stream being processed in said first instruction pipeline, for activating at least a portion of said second instruction pipeline in a first mode in which said second decoder stage and said second execute stage operate upon instructions retrieved by said first fetch stage while said first decoder stage and said first execute stage also operate upon said instructions retrieved by said first fetch stage, wherein said second fetch stage is deactivated when said single digital processor is in said first mode. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22)
a common instruction memory directly coupled to both said first and second fetch stages.
-
-
20. An integrated circuit as set forth in claim 1 wherein said first instruction includes a Cfork instruction.
-
21. An integrated circuit as set forth in claim 1 wherein said single digital processor further comprises:
a common data memory, coupled to both said first and second execute stages, for storing data and processed data output from said first and second execute stages.
-
22. An integrated circuit as set forth in claim 4 wherein said second instruction includes a Cjoin instruction.
-
23. A method of processing data in a single digital processor for switching between different modes of operation, said single digital processor having a common instruction memory and first and second instruction pipelines, said first instruction pipeline comprising at least a first fetch stage, a first decoder stage and a first execute stage, said second instruction pipeline comprising a second fetch stage, a second decoder stage and a second execute stage, said method comprising the steps of:
-
(1) operating in a first mode in which said first instruction pipeline is fully operational to execute instructions retrieved from said common instruction memory and said second instruction pipeline is deactivated;
(2) activating at least a portion of said second instruction pipeline in a second mode, responsive to a first instruction being processed in said first instruction pipeline, in which said decoder stage and said execute stage of said second instruction pipeline operate upon instructions retrieved by said first fetch stage of said first instruction pipeline while said first decoder stage and said first execute stage also operate upon said instructions retrieved by said first fetch stage; and
(3) deactivating said second decoder stage and said second execute stage responsive to a second instruction in said second instruction pipeline. - View Dependent Claims (24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34)
(4) activating said second fetch stage, said second decoder stage and said second execute stage responsive to a third instruction in said first instruction pipeline, whereby said first and second instruction pipelines can operate on separate instruction streams simultaneously.
-
-
25. A method as set forth in claim 24 wherein said third instruction includes an operand field containing an address of an instruction at which said second instruction pipeline is to commence executing instructions, said method further comprising the step of:
(5) providing said address from said first decoder stage of said first instruction pipeline to said second fetch stage of said second instruction pipeline.
-
26. A method as set forth in claim 25 further comprising the step of:
(6) deactivating said second fetch stage, said second decoder stage and said second execute stage responsive to a fourth instruction in said second instruction pipeline.
-
27. A method as set forth in claim 26 further comprising the step of:
(7) responsive to a fifth instruction in said first instruction pipeline, suspending execution of a next instruction in said first instruction pipeline, pending receipt of said fourth instruction in said second instruction pipeline, such that execution of instructions in said first instruction pipeline can be suspended pending creation of data in said second instruction pipeline.
-
28. A method set forth in claim 26 wherein said second instruction pipeline includes a plurality of second instruction pipeline and wherein steps (2), (3), (4) and (6) include the step of:
(9) specifying a particular instruction pipeline to which the instruction pertains.
-
29. A method as set forth in claim 28 wherein step (9) includes the step of:
specifying a particular instruction pipeline in which said fourth instruction must be received in order to recommence the execution of instructions in said first instruction pipeline.
-
30. A method as set forth in claim 23 wherein, in said deactivating step (3), said second instruction includes a Cjoin instruction.
-
31. A method as set forth in claim 23 further comprising the step of:
(8) introducing a delay in said second instruction pipeline so as to offset execution of instructions in said first and second instruction pipelines, wherein said delay is in said second decoder stage of said second instruction pipeline.
-
32. A method as set forth in claim 23 further comprising:
(10) loading, by instructions processed in said first instruction pipeline, data stored in at least one register of said first execute stage into at least one register of said second execute stage.
-
33. A method as set forth in claim 32 wherein, in said loading step (10), said instructions processed in said first instruction pipeline include a MOV AtoB instruction.
-
34. A method as set forth in claim 23 wherein, in said activating step (2), said first instruction includes a Cfork instruction.
-
35. A single digital processor comprising:
-
a first instruction pipeline comprising a first fetch stage, a first decoder stage, and a first execute stage, for processing data responsive to an instruction stream;
a second instruction pipeline comprising a second fetch stage, a second decoder stage, and a second execute stage, for processing data responsive to an instruction stream; and
control means, responsive to a first instruction in an instruction stream being processed in said first instruction pipeline, for activating said second fetch stage, said second decoder stage and said second execute stage in a first mode, whereby said first and second pipelines operate on separate instructions simultaneously, wherein, prior to receipt of said first instruction in an instruction stream being processed in said first instruction pipeline, said single digital processor operates in a second mode in which said first instruction pipeline is fully operational and said second instruction pipeline is deactivated except for said at least one register of said second execute stage. - View Dependent Claims (36, 37, 38, 39, 40, 41, 42, 43)
-
-
44. A single digital processor for switching between different modes of operation, said single digital processor comprising:
-
a common instruction memory for storing therein at least first and second instructions streams;
a first instruction pipeline for executing said first instruction stream stored in said common instruction memory, said first instruction pipeline including a first fetch stage for retrieving said first instruction stream from said common instruction memory, a first decoder stage for decoding said first instruction stream retrieved by said first fetch stage, and a first execute stage for executing said first instruction stream decoded by said first decoder stage;
at least one second instruction pipeline for executing either said first instruction stream obtained from said first instruction pipeline or said second instruction stream obtained from said common instruction memory, said second instruction pipeline including a second fetch stage for retrieving said second instruction stream from said common instruction memory, a selecting unit for selectively receiving one of said second instruction stream from said second fetch stage and said first instruction stream from said first fetch stage, a second decoder stage for decoding one of said first and second instruction streams from said selecting unit, and a second execute stage for executing said instruction stream decoded by said second decoder stage;
a controller for activating at least a portion of said second instruction pipeline responsive to a first instruction being processed in said first instruction pipeline, so that said second instruction pipeline can execute one of said first and second instruction streams; and
a common data memory, coupled to both said first and second execute stages, for storing data and processed data output from said first and second execute stages. - View Dependent Claims (45, 46, 47, 48)
-
Specification