Systems and methods for protecting access to encrypted information

• US 6,272,637 B1
• Filed: 04/14/1997
• Issued: 08/07/2001
• Est. Priority Date: 04/14/1997
• Status: Expired due to Term

• Current Assignee: Maxim Integrated Products, Inc. (Analog Devices, Inc.)
• Original Assignee: Dallas Semiconductor Corporation (Analog Devices, Inc.)
• Inventors: Little, Wendell L., Loomis, Donald W., Curry, Stephen M.
• Primary Examiner(s): Swann, Tod
• Assistant Examiner(s): Meislahn, Douglas J.
• Application Number:
  US08/837,145
• Time in Patent Office: 1,576 Days
• Field of Search: 380/3, 380/4, 380/52, 711/166, 713/193, 713/194
• US Class Current: 713/194
• CPC Class Codes: G06F 12/1408 by using cryptography for digital transmission H04L9/00
• CPC Class Codes: G06F 21/554 involving event detection and direct action
• CPC Class Codes: G06F 21/72 in cryptographic circuits
• CPC Class Codes: G06F 2207/7219 Countermeasures against side channel or fault attacks
• CPC Class Codes: G11C 29/46 Test trigger logic

Abstract

A microcontroller communicating via a data path and an address path with a memory block containing encrypted contents, the microcontroller including the capability for detecting resets effectuated in the wake of an unauthorized attempt to gain access to the encrypted contents and the capability of evading such an unauthorized attempt.

Claims

1. A system including a first circuit with an internal bus, said first circuit being capable of communicating with a second circuit via a data bus and an address bus, said second circuit including an external memory block, said system comprising:

a detector for detecting an uncompensated system reset;

means for determining whether said detected uncompensated system reset includes an attacking uncompensated system reset, said means for determining further for determining whether said uncompensated system reset was initiated responsive to an environmental condition, thereby indicating that said uncompensated system reset includes a non-attacking uncompensated system reset;

a storage device connected to said detector, said storage device including a system reset indicator value, wherein said system reset indicator value is indicative of a number of detected attacking uncompensated system resets;

means for incrementing said system reset indicator value included in said storage device responsive to detecting said uncompensated system reset and responsive to determining that said detected uncompensated system reset is said attacking uncompensated system reset;

means for launching an evasive action responsive to said system reset indicator value being equal to or greater than a threshold;

a secure memory block, disposed within said first circuit, said secure memory block being coupled to said internal bus;

an address path encryptor for encrypting signals asserted on said address bus using the contents of a first encryption key, said address path encryptor being coupled to said internal bus;

a data path encryptor for encrypting signals asserted on said data bus using the contents of a second encryption key, said data path encryptor being coupled to said internal bus; and

a power input;

wherein said means for determining whether said uncompensated system reset was initiated responsive to an environmental condition comprises;

means for monitoring said power input to determine whether an uncompensated system reset is initiated responsive to a power fluctuation, wherein the power fluctuation is associated with a power fluctuation frequency and wherein said means for monitoring is configured to monitor said power fluctuation frequency.

2. The system as set forth in claim 1, wherein said storage device comprises:

a special function register for storing said system reset indicator value, said special function registered configured such that said system reset indicator value is not altered responsive to the detected uncompensated system reset, wherein said detected uncompensated system reset is a non-attacking uncompensated system reset; and

a reset-threshold register, wherein each of said special function register and reset-threshold register is coupled to said internal bus.

3. The system as set forth in claim 2, wherein said means for launching comprises:

means for comparing the system reset indicator value with the contents of said reset-threshold register; and

means for effectuating a loop within said secure memory block, said structure for effectuating being responsive to a signal generated by said means for comparing.

4. The system as set forth in claim 2, wherein said means for launching comprises:

an access register, coupled to said internal bus;

means for comparing said system reset indicator value with the contents of said reset-threshold register; and

means for erasing the contents of said second circuit, said means for erasing being responsive, at least in part, to the contents of said system reset indicator value.

5. The system including a first circuit with an internal bus, said first circuit being capable of communication with a second circuit via a data bus and an address bus, said second circuit including an external memory block, said system comprising:

a detector for detecting an uncompensated system reset;

means for determining whether said detected uncompensated system reset includes an attacking uncompensated system reset;

a storage device connected to said detector, said storage device including a system reset indicator value, wherein said system reset indicator value is indicative of a number of detected attacking uncompensated system resets;

means for incrementing said system reset indicator value included in said storage device responsive to detecting an uncompensated system reset and respinsive to determining that said detected uncompensated system reset includes said attacking uncompensated system reset; and

means for launching an evasive action responsive to said system reset imdicator value reaching a threshold;

a power input;

and further wherein said means for determining whether said uncompensated system reset was initiated responsive to an environmental condition, thereby indicating that said uncompensated system reset includes a non-attacking uncompensated system reset and further wherein said means for determining comprises

means for monitoring said power input to determine whether an uncompensated system reset is initiated to a power fluctuation, thereby indicating that said uncompensated system reset includes said non-attacking uncompensated system reset; and

wherein said means for monitoring said power input includes;

means for monitoring a frequency of said power fluctuation.