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Method for cell swapping to improve pre-layout to post-layout timing

  • US 6,272,668 B1
  • Filed: 05/25/1999
  • Issued: 08/07/2001
  • Est. Priority Date: 12/14/1994
  • Status: Expired due to Term
First Claim
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1. A method for improving the timing performance of an ASIC layout, said ASIC having at least one standard cell circuit component and at least one timing arc associated with said standard cell circuit component, said method comprising the steps of:

  • placing all circuits in the ASIC layout;

    routing all timing arcs in the ASIC layout;

    generating a pre-layout timing target value for a timing arc of said ASIC automatically based on historical statistical information regarding the ASIC layout before said placing and routing steps;

    determining a post-layout timing value for said timing arc after said placing and routing steps;

    calculating a timing slack value for said timing arc by subtracting said post-layout timing value from said pre-layout timing target value;

    repeating said generating a pre-layout timing, determining a post-layout timing and calculating a timing slack value steps for each timing arc of each standard cell circuit component in order to generate a list of at least one timing slack value which corresponds to each timing arc;

    determining a timing difference between the standard cell circuit component associated with a timing arc in said list and at least one logically equivalent second standard cell circuit component;

    calculating a slack change value by subtracting said timing difference from the timing slack value associated with the said timing arc in said list;

    repeating said determining a timing difference and calculating a slack change value steps for each second standard cell circuit component logically equivalent to said standard cell circuit component;

    identifying which said slack change value, calculated by operation of said step of repeating said determining a timing difference and calculating a slack change value steps, most improves performance of said ASIC with respect to said timing arc on said list in order to generate an optimum timing slack value;

    swapping said standard cell circuit component associated with said timing arc on said list with the second standard cell circuit component associated with said optimum timing slack value to improve timing performance of said ASIC layout; and

    repeating said steps of determining a timing difference, calculating a slack change value, repeating said determining a timing difference and calculating a slack change value steps for each second standard cell circuit component, identifying, and swapping for each timing arc on said list.

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