Method for cell swapping to improve pre-layout to post-layout timing
First Claim
1. A method for improving the timing performance of an ASIC layout, said ASIC having at least one standard cell circuit component and at least one timing arc associated with said standard cell circuit component, said method comprising the steps of:
- placing all circuits in the ASIC layout;
routing all timing arcs in the ASIC layout;
generating a pre-layout timing target value for a timing arc of said ASIC automatically based on historical statistical information regarding the ASIC layout before said placing and routing steps;
determining a post-layout timing value for said timing arc after said placing and routing steps;
calculating a timing slack value for said timing arc by subtracting said post-layout timing value from said pre-layout timing target value;
repeating said generating a pre-layout timing, determining a post-layout timing and calculating a timing slack value steps for each timing arc of each standard cell circuit component in order to generate a list of at least one timing slack value which corresponds to each timing arc;
determining a timing difference between the standard cell circuit component associated with a timing arc in said list and at least one logically equivalent second standard cell circuit component;
calculating a slack change value by subtracting said timing difference from the timing slack value associated with the said timing arc in said list;
repeating said determining a timing difference and calculating a slack change value steps for each second standard cell circuit component logically equivalent to said standard cell circuit component;
identifying which said slack change value, calculated by operation of said step of repeating said determining a timing difference and calculating a slack change value steps, most improves performance of said ASIC with respect to said timing arc on said list in order to generate an optimum timing slack value;
swapping said standard cell circuit component associated with said timing arc on said list with the second standard cell circuit component associated with said optimum timing slack value to improve timing performance of said ASIC layout; and
repeating said steps of determining a timing difference, calculating a slack change value, repeating said determining a timing difference and calculating a slack change value steps for each second standard cell circuit component, identifying, and swapping for each timing arc on said list.
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Accused Products
Abstract
A method for improving the timing performance of a standard cell ASIC layout. The method is operable at any phase of the ASIC design cycle including following the completion of layout phase placement and routing. The method compares post-layout timing values with pre-layout timing targets for each timing arc associated with each standard cell component of the ASIC design. For each timing arc, a functionally equivalent cell having higher or lower output drive is selected which optimally improves the timing slack on each timing arc. To assure that the method converges and terminates, a list of timing slack values, one for each timing arc of the ASIC design, is constructed in sorted order from worst timing slack to best timing slack. The swap method determines in order from worse timing slack to best a functionally equivalent standard cell which may be swapped to improve the timing slack on the timing arc. Once a standard cell is swapped for a given timing arc, no further swaps need be made for subsequent entries on the sorted list: the timing slack of subsequent entries is assured to be better than the worse timing slack value of an earlier encountered timing arc in the sorted list.
130 Citations
23 Claims
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1. A method for improving the timing performance of an ASIC layout, said ASIC having at least one standard cell circuit component and at least one timing arc associated with said standard cell circuit component, said method comprising the steps of:
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placing all circuits in the ASIC layout;
routing all timing arcs in the ASIC layout;
generating a pre-layout timing target value for a timing arc of said ASIC automatically based on historical statistical information regarding the ASIC layout before said placing and routing steps;
determining a post-layout timing value for said timing arc after said placing and routing steps;
calculating a timing slack value for said timing arc by subtracting said post-layout timing value from said pre-layout timing target value;
repeating said generating a pre-layout timing, determining a post-layout timing and calculating a timing slack value steps for each timing arc of each standard cell circuit component in order to generate a list of at least one timing slack value which corresponds to each timing arc;
determining a timing difference between the standard cell circuit component associated with a timing arc in said list and at least one logically equivalent second standard cell circuit component;
calculating a slack change value by subtracting said timing difference from the timing slack value associated with the said timing arc in said list;
repeating said determining a timing difference and calculating a slack change value steps for each second standard cell circuit component logically equivalent to said standard cell circuit component;
identifying which said slack change value, calculated by operation of said step of repeating said determining a timing difference and calculating a slack change value steps, most improves performance of said ASIC with respect to said timing arc on said list in order to generate an optimum timing slack value;
swapping said standard cell circuit component associated with said timing arc on said list with the second standard cell circuit component associated with said optimum timing slack value to improve timing performance of said ASIC layout; and
repeating said steps of determining a timing difference, calculating a slack change value, repeating said determining a timing difference and calculating a slack change value steps for each second standard cell circuit component, identifying, and swapping for each timing arc on said list. - View Dependent Claims (2, 3)
wherein said step of repeating said generating, determining and calculating steps further comprises the step of sorting said list in ascending numerical order of said timing slack values;
wherein said swapping step further comprises the step of noting that said timing arc associated with said second standard cell circuit component is associated with a swapped component; and
wherein said step of repeating said determining, calculating, repeating, identifying, and swapping steps further comprises the steps of;
determining whether said timing arc on said list is noted to be associated with a swapped component, and skipping the step of repeating said determining, calculating, repeating, identifying, and swapping steps for said timing arc on said list determined to be associated with a swapped component.
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3. The method of claim 1 further comprising the step of overriding one or more of said automatically generated pre-layout timing target value by entering a replacement pre-layout timing target value for any timing arc.
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4. A method for improving the performance of an ASIC layout with respect to a predetermined parameter, said ASIC having at least one standard cell circuit component and at least one timing arc associated with said standard cell circuit component, said method comprising the steps of:
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placing all circuits in the ASIC layout;
routing all timing arcs in the ASIC layout;
generating a pre-layout timing target value for a timing arc of said ASIC automatically based on historical statistical information regarding the ASIC layout before said placing and routing steps;
determining a post-layout timing value for said timing arc after said placing and routing steps;
calculating a performance slack value for said timing arc by subtracting said post-layout timing value from said pre-layout timing target value;
repeating said generating a pre-layout timing target value, determining a post-layout timing value and calculating a performance slack value steps for each timing arc for each standard cell circuit component in order to generate a list of at least one performance slack value which corresponds to each timing arc;
determining a performance difference between the standard cell circuit component associated with a timing arc in said list and at least one logically equivalent second standard cell circuit component;
calculating a slack change value by subtracting said performance difference from the performance slack value associated with the said timing arc in said list;
repeating said determining a performance difference and calculating a slack change value steps for each second standard cell circuit component logically equivalent to said standard cell circuit component;
identifying which said slack change value calculated by operation of said step of repeating said determining a performance difference and calculating a slack change value steps, most improves performance of said ASIC with respect to said predetermined parameter of said timing arc on said list in order to generate an optimum performance slack value;
swapping said standard cell circuit component associated with said timing arc on said list with the second standard cell circuit component associated with said optimum performance slack value to improve performance of said ASIC layout with respect to said predetermined parameter; and
repeating said steps of determining a performance difference, calculating a slack change value, repeating said determining a performance difference and calculating a slack change value steps for each second standard cell circuit component, identifying, and swapping for each timing arc on said list. - View Dependent Claims (5, 6, 7, 8)
wherein said step of repeating said generating, determining and calculating steps further comprises the step of sorting said list in ascending numerical order of said performance slack values;
wherein said swapping step further comprises the step of noting that said timing arc associated with said second standard cell circuit component is associated with a swapped component; and
wherein said step of repeating said determining, calculating, repeating, identifying, and swapping steps further comprises the steps of;
determining whether said timing arc on said list is noted to be associated with a swapped component, and skipping said step of repeating said determining, calculating, repeating, identifying, and swapping steps for said timing arc on said list determined to be associated with a swapped component.
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6. The method of claim 4 wherein said predetermined parameter is the capacitive load of said timing arc.
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7. The method of claim 4 wherein said predetermined parameter is the timing of signals on said timing arc.
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8. The method of claim 4 wherein said predetermined parameter is the power dissipation on said timing arc.
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9. A method of improving the timing performance of an ASIC layout, said ASIC having at least one standard cell circuit component and at least one timing arc associated with said standard cell circuit component, said method comprising the steps of:
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placing all circuits in the ASIC layout;
routing all timing arcs in the ASIC layout;
generating a pre-layout timing target value for a timing arc of said ASIC automatically based on historical statistical information regarding the ASIC layout before said placing and routing steps;
determining a post-layout timing value for said timing arc after said placing and routing steps;
comparing the pre-layout timing target value for each timing arc with the post-layout timing value for each timing arc;
selecting a second standard cell circuit component logically equivalent to the standard cell circuit component associated with each timing arc, wherein said second standard cell component improves the timing performance of each timing arc; and
swapping each second standard cell component selected by operation of said selecting step with the standard cell circuit component associated with each timing arc. - View Dependent Claims (10)
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11. A method for improving the performance of an ASIC layout with respect to a predetermined parameter, said ASIC having at least one standard cell circuit component and at least one timing arc associated with said standard cell circuit component, said method comprising the steps of:
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placing all circuits in the ASIC layout;
routing all timing arcs in the ASIC layout;
generating a pre-layout performance target value for a timing arc of said ASIC automatically based on historical statistical information regarding the ASIC layout before said placing and routing steps;
determining a post-layout performance value for said timing arc after said placing and routing steps;
comparing the pre-layout performance target value for each timing arc with the post-layout performance value for each timing arc;
selecting a second standard cell circuit component logically equivalent to the standard cell circuit component associated with each timing arc, wherein said second standard cell component improves the performance of each timing arc with respect to said predetermined parameter; and
swapping each second standard cell component selected by operation of said selecting step with the standard cell circuit component associated with each timing arc. - View Dependent Claims (12, 13, 14, 15)
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16. A method for improving the performance of an ASIC layout with respect to a predetermined parameter, said ASIC having at least one circuit component and at least one timing arc associated with said at least one circuit component said method comprising the steps of:
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placing all circuits in the ASIC layout;
routing all timing arcs in the ASIC layout;
generating a pre-layout timing target value for a timing arc of said ASIC automatically based on historical statistical information regarding the ASIC layout before said placing and routine steps;
determining a post-layout timing value for said timing arc after said placing and routing steps;
calculating a performance slack value for said timing arc by subtracting said post-layout timing value from said pre-layout timing target value;
repeating said generating a pre-layout timing target value, determining a post-layout timing value and calculating a performance slack value steps for each timing arc for each circuit component in order to generate a list of at least one performance slack value which corresponds to each timing arc;
determining a performance difference between the circuit component associated with a timing arc in said list and at least one logically equivalent second circuit component;
calculating a slack change value by subtracting said performance difference from the performance slack value associated with the said timing arc in said list;
repeating said determining a performance difference and calculating a slack change value steps for each second circuit component logically equivalent to said circuit component;
identifying which said slack change value,calculated by operation of said step of repeating said determining a performance difference and calculating a slack change value steps, most improves performance of said ASIC with respect to said predetermined parameter of said timing arc on said list in order to generate an optimum performance slack value;
swapping said circuit component associated with said timing arc on said list with the second circuit component associated with said optimum performance slack value to improve performance of said ASIC layout with respect to said predetermined parameter; and
repeating said steps of determining a performance difference, calculating a slack change value, repeating said determining a performance difference and calculating a slack change value steps for each second circuit component, identifying, and swapping for each timing arc on said list. - View Dependent Claims (17, 18, 19, 20, 21)
wherein said step of repeating said generating, determining and calculating steps further comprises the step of sorting said list in ascending numerical order of said performance slack values;
wherein said swapping step further comprises the step of noting that said timing arc associated with said second circuit component is associated with a swapped component; and
wherein step of repeating said determining, calculating, repeating, identifying, and swapping steps further comprises the steps of;
determining whether said timing arc on said list is noted to be associated with a swapped component, and skipping said step of repeating said determining, calculating, repeating, identifying, and swapping steps for said timing arc on said list determined to be associated with a swapped component.
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18. The method of claim 16 wherein said predetermined parameter is the capacitive load of said timing arc.
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19. The method of claim 16 wherein said predetermined parameter is the timing of signals on said timing arc.
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20. The method of claim 16 wherein said predetermined parameter is the power dissipation on said timing arc.
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21. The method of claim 16 further comprising the step of overriding one or more of said automatically generated pre-layout timing target value by entering a replacement pre-layout timing target value for any timing arc.
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22. A method for improving, performance of an integrated circuit layout having, a plurality of internal cells coupled by internal signals therebetween, comprising the steps of:
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placing the plurality internal cells in the integrated circuit layout;
routing, all internal signals in the integrated circuit layout;
generating a pre-layout timing target for said internal signals of said integrated circuit automatically based on historical statistical information regarding the integrated circuit layout before said placing and routing steps;
determining a post-layout signal timing for said internal signals after said placing and routing steps;
comparing the post-layout signal timing with pre-layout timing target; and
replacing at least one of the internal cells with a different cell when the post-layout signal timing does not conform to the pre-layout timing target. - View Dependent Claims (23)
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Specification