Method for forming a capacitor electrode

• US 6,274,424 B1
• Filed: 06/23/2000
• Issued: 08/14/2001
• Est. Priority Date: 11/03/1997
• Status: Expired due to Term

• Current Assignee: North Star Innovations Inc. (Wi-LAN Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: White, Jr., Bruce E., Jones, Jr., Robert Edwin
• Primary Examiner(s): Bowers, Charles
• Assistant Examiner(s): Huynh, Yennhu B.
• Application Number:
  US09/602,785
• Time in Patent Office: 417 Days
• Field of Search: 438/239, 438/597, 438/618, 438/396, 438/3, 438/240, 438/253-256, 438/393-398, 438/295
• US Class Current: 438/239
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 28/55 with a dielectric comprising a perovskite structure material
• CPC Class Codes: H01L 28/60 Electrodes
• CPC Class Codes: H10B 12/033 the capacitor extending over the transistor
• CPC Class Codes: H10B 12/05 Making the transistor

Abstract

A method for forming an improved embedded DRAM structure, that is formed on-chip with CMOS logic portions, begins by forming dual inlaid regions (34a through 34c). The region (34a) is a portion of a dual inlaid region which is filled with an oxidation tolerant material (e.g., iridium or ruthenium) to form a metallic plug (36a). This plug (36a) forms a storage node region for a DRAM and electrically contacts to a current electrode (26) of a DRAM pass transistor. Opening (34b) is filled concurrently with the filling of opening (34a), to form a metallic plug (36b) which forms a bit line contact for the DRAM cell. A top portion of the dual inlaid structure (34c) is filled concurrent with regions (34a and 34b) to enable formation of a bottom electrode of the ferroelectric DRAM capacitor. Since the geometry of the region (36c) is defined by dual inlaid/CMP processing, no RIE-defined sidewall of the bottom capacitor electrode is present whereby capacitor leakage current is reduced. Furthermore, the oxygen-tolerant material used to form the plugs (36a through 36c) herein prevents adverse plug oxidation which is present in the prior art during ferroelectric oxygen annealing.

Claims

1. A method of forming a semiconductor structure, the method comprising the steps of:

forming a first dielectric layer;

forming a first opening in the first dielectric layer;

depositing a first metallic layer in the first opening;

planarizing the first metallic layer to form a first conductive plug in the first opening;

forming a second dielectric layer over the first conductive plug;

forming a second opening in the second dielectric layer, the second opening exposing a top portion of the first conductive plug;

depositing a second metallic layer in the second opening;

planarizing the second metallic layer to form a second conductive plug in the second opening;

forming a third dielectric layer over the second conductive plug;

forming a third opening in the third dielectric layer, the third opening exposing a top portion of the second conductive plug;

depositing a third metallic layer in the third opening;

planarizing the third metallic layer to form a third conductive plug in the third opening; and

wherein the first, second, and third conductive plugs collectively form a DRAM storage node between a current electrode of a transistor and a DRAM capacitor dielectric.

2. The method of claim 1 wherein the steps of forming the first, second, and third metallic layers comprise:

forming the first metallic layer comprising tungsten, forming the second metallic layer comprising an oxygen-tolerant metallic, and forming the third metallic layer comprising platinum.

3. The method of claim 2 wherein the steps of forming the second metallic layer comprises:

forming the second metallic layer comprising iridium.

4. The method of claim 1 wherein the steps of forming the third metallic layer comprises:

forming the third conductive plug in close proximity to a high-k capacitor dielectric layer wherein the third conductive plug functions as a capacitor electrode.

5. The method of claim 4 wherein the steps of forming the third metallic layer comprises:

forming the third conductive plug as a bottom conductive capacitor electrode for a ferroelectric DRAM capacitor which is embedded on-chip with a microprocessor.

6. A method of forming a semiconductor structure, the method comprising the steps of:

forming a first dielectric layer;

forming a first opening in the first dielectric layer;

depositing a first metallic layer in the first opening;

planarizing the first metallic layer to form a first conductive plug in the first opening;

forming a dual inlaid opening in the second dielectric layer wherein the dual inlaid opening exposes a portion of the first conductive plug;

depositing a second metallic layer in the dual inlaid opening;

planarizing the second metallic layer to form a second conductive plug in the dual inlaid opening;

etching the second conductive plug to vertically recess the second conductive plug into the dual inlaid opening thereby forming a recess region;

depositing a third metallic layer in the recess region; and

planarizing the third metallic layer to form a third conductive plug over the second conductive plug.

7. The method of claim 6 wherein the step of planarizing the third metallic layer to form a third conductive plug comprises:

forming a third conductive plug as a bottom capacitor electrode for a capacitor.

8. The method of claim 7 wherein the step of planarizing the third metallic layer to form a third conductive plug comprises:

forming the the third conductive plug as a bottom capacitor electrode wherein the capacitor is a high-k dielectric capacitor.

9. The method of claim 8 further comprising:

forming the capacitor on-chip with a CMOS logic area.

10. The method of claim 6 wherein the steps of forming the first, second, and third metallic layers comprise:

forming the first metallic layer comprising tungsten, forming the second metallic layer comprising an oxygen-tolerant metallic, and forming the third metallic region comprising platinum.

11. The method of claim 10 wherein the steps of forming second metallic layer comprises:

forming the second metallic layer comprising ruthenium.

12. The method of claim 6 wherein the steps of forming second metallic layer comprises:

forming the second metallic layer as a material which is etched in an oxygen environment.

13. The method of claim 6 wherein the first, second, and third conductive plugs collectively form a storage node for a DRAM capacitor wherein the storage node couples to a pass transistor.