Fabrication method for a high voltage electrical erasable programmable read only memory device

• US 6,274,430 B1
• Filed: 07/26/2000
• Issued: 08/14/2001
• Est. Priority Date: 07/07/2000
• Status: Expired due to Term

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Hsu, Sung-Mu, Jan, Yi-Peng
• Primary Examiner(s): CHAUDHARI, CHANDRA P
• Application Number:
  US09/625,565
• Time in Patent Office: 384 Days
• Field of Search: 437/258, 437/266, 437/267, 437/275, 437/286, 437/981
• US Class Current: 438/258
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/49 comprising different types of peripheral transistor

Abstract

A fabrication method for a high voltage electrically erasable read only memory is described, wherein a substrate comprising a memory device region and a peripheral high voltage circuit region is provided. A floating gate is formed on the substrate in the device region, while a gate electrode is formed on the substrate in the peripheral circuit region. Thereafter, an oxide/nitride/oxide layer is formed on the substrate, wherein the oxide/nitride/oxide layer is formed by stacking from bottom to top a first oxide layer, a nitride layer and a second oxide layer. The second oxide layer in the peripheral high voltage circuit region is then removed, followed by removing the nitride layer in the peripheral high voltage circuit region. An oxidation on the second oxide layer and a double diffused drain implantation are conducted to form a bird'"'"'s beak structure at the bottom corner of the gate electrode and to form a double diffused drain structure in the substrate on both sides of the gate electrode. A control gate is then formed on the oxide/nitride/oxide layer of the device region and a gate electrode is formed in the peripheral low voltage circuit region. Subsequently, a source/drain region is formed in the substrate on both sides of the gate electrode in the peripheral low voltage circuit region.

Claims

1. A fabrication method for a high voltage electrically erasable read only memory device comprising the steps of:

providing a substrate, wherein the substrate comprises a memory device region and a peripheral high voltage circuit region and a peripheral low voltage circuit region, wherein a floating gate and a select-gate are formed on the substrate in the memory device region, and a high voltage gate electrode is formed on the substrate in the peripheral high voltage circuit region;

forming an oxide/nitride/oxide layer on the substrate, wherein the oxide/nitride/oxide layer is formed by stacking from bottom to top a first oxide layer, a nitride layer and a second oxide layer;

forming a patterned photoresist layer on the substrate, wherein the patterned photoresist layer exposes the oxide/nitride/oxide layer in the peripheral high voltage circuit region and a portion of the memory device region;

removing the second oxide layer in the peripheral high voltage circuit region and a portion of the second oxide layer in the memory device region;

removing the patterned photoresist layer;

removing the nitride layer in the peripheral high voltage circuit region and a portion of the nitride layer in the memory device region;

performing an oxidation process on a bottom corner of the gate electrode, wherein the first oxide layer is oxidized and a bird'"'"'s beak structure is formed at the bottom corner of the gate electrode;

removing the oxide-nitride-oxide layer in the peripheral low voltage circuit region;

conducting a double diffused drain ion implantation process to form a double diffused drain structure in the substrate on both sides of the high voltage gate electrode in the peripheral high voltage circuit region;

forming a first source/drain region that comprises the double diffused drain structure on both sides of the gate electrode in the substrate, and a second source/drain region on one side of the floating gate in the substrate;

forming a gate oxide layer on the peripheral low voltage circuit region;

forming a control gate on the oxide/nitride/oxide layer of the memory device region and low voltage gate electrode on the gate oxide layer of the peripheral low voltage circuit region; and

forming a third source/drain region on the substrate on both sides of the low voltage gate electrode.

2. The fabrication method according to claim 1, wherein a photomask used to form the patterned photoresist layer is a same mask used in the double diffused drain implantation process.

3. The fabrication method according to claim 1, wherein the oxidation process performed on the bottom corner of the gate electrode includes a thermal oxidation process.

4. The fabrication method according to claim 1, wherein removing the second oxide layer includes using a solution containing fluorinated helium to remove the second oxide layer.

5. The fabrication method according to claim 1, wherein removing the nitride layer includes using a hot phosphoric acid solution to etch the nitride layer.

6. The fabrication method according to claim 1, wherein the oxidation process on the gate electrode bottom corner and a formation of the gate oxide layer on the peripheral low voltage circuit region are accomplished in a same thermal oxidation process.

7. A fabrication method for a high voltage electrically erasable read only memory device, which is applicable on a substrate and the substrate comprises a memory device region and a peripheral high voltage circuit region, wherein a floating gate and a select-gate are formed on the substrate in the memory device region and a gate electrode is formed on the substrate in the peripheral high voltage circuit region, the method comprising:

forming an oxide/nitride/oxide layer on the substrate;

forming a patterned photoresist layer on the substrate, wherein the patterned photoresist layer exposes the oxide/nitride/oxide layer in the peripheral high voltage circuit region and a portion of the oxide/nitride/oxide layer in the memory device region;

removing a portion of an upper oxide layer of the oxide/nitride/oxide layer using the photoresist layer as a mask;

removing the patterned photoresist layer;

removing a portion of the nitride layer of the oxide/nitride/oxide layer;

performing a double diffused ion implantation to form a double diffused drain structure in the substrate on both sides of the gate electrode;

oxidizing an lower oxide layer of the oxide/nitride/oxide layer to form a bird'"'"'s beak structure at a bottom corner of the gate electrode;

forming a control gate on the oxide/nitride/oxide layer in the device region, wherein the control gate, the oxide/nitride/oxide layer, and the floating gate form an electrically erasable read only memory having a split gate; and

forming a first source/drain region that comprises the double diffused drain structure in the substrate on both sides of the gate electrode, and a second source/drain region in the substrate on one side of the floating gate.

8. The fabrication method according to claim 7, wherein a photomask used to form the patterned photoresist layer is same mask used for the double diffused drain ion implantation process.

9. The fabrication method according to claim 7, wherein forming the bird'"'"'s beak structure includes performing a thermal oxidation process.

10. The fabrication method according to claim 7, wherein removing the upper oxide layer includes using a solution containing fluorinated helium to remove the upper oxide layer.

11. The fabrication method according to claim 7, wherein the nitride layer is removed by etching with a hot phosphoric acid solution.

12. A fabrication method for a high voltage electrically erasable read only memory, which is applicable on a substrate and the substrate comprises a memory device region and a peripheral high voltage circuit region, wherein a floating gate is formed on the substrate in the memory device region and a gate electrode is formed on the substrate in the peripheral high voltage circuit region, comprising

forming an oxide/nitride/oxide layer on the substrate, wherein the oxide/nitride/oxide layer is formed by stacking from bottom to top a first oxide layer, a nitride layer and a second oxide layer;

removing the second oxide layer in the peripheral high voltage circuit region;

removing the nitride layer in the peripheral high voltage circuit region;

oxidizing the first oxide layer and performing a double diffused drain implantation to form a bird'"'"'s beak structure at a bottom corner of the gate electrode and to form a double diffused drain structure in the substrate on both sides of the gate electrode;

forming a control gate on the oxide/nitride/oxide layer in the memory device region; and

forming a first source/drain region that comprises the double diffused drain structure in the substrate on both sides of the gate electrode, and a second source/drain region in the substrate on one side of the floating gate.

13. The fabrication method according to claim 12, wherein forming the bird'"'"'s beak structure includes performing a thermal oxidation process.

14. The fabrication method according to claim 12, wherein removing the second oxide layer includes using a solution containing fluorinated helium to remove the second oxide layer.

15. The fabrication method according to claim 12, wherein removing the nitride layer includes using a hot phosphoric acid solution to etch the nitride layer.