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Fabrication method for a high voltage electrical erasable programmable read only memory device

  • US 6,274,430 B1
  • Filed: 07/26/2000
  • Issued: 08/14/2001
  • Est. Priority Date: 07/07/2000
  • Status: Expired due to Term
First Claim
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1. A fabrication method for a high voltage electrically erasable read only memory device comprising the steps of:

  • providing a substrate, wherein the substrate comprises a memory device region and a peripheral high voltage circuit region and a peripheral low voltage circuit region, wherein a floating gate and a select-gate are formed on the substrate in the memory device region, and a high voltage gate electrode is formed on the substrate in the peripheral high voltage circuit region;

    forming an oxide/nitride/oxide layer on the substrate, wherein the oxide/nitride/oxide layer is formed by stacking from bottom to top a first oxide layer, a nitride layer and a second oxide layer;

    forming a patterned photoresist layer on the substrate, wherein the patterned photoresist layer exposes the oxide/nitride/oxide layer in the peripheral high voltage circuit region and a portion of the memory device region;

    removing the second oxide layer in the peripheral high voltage circuit region and a portion of the second oxide layer in the memory device region;

    removing the patterned photoresist layer;

    removing the nitride layer in the peripheral high voltage circuit region and a portion of the nitride layer in the memory device region;

    performing an oxidation process on a bottom corner of the gate electrode, wherein the first oxide layer is oxidized and a bird'"'"'s beak structure is formed at the bottom corner of the gate electrode;

    removing the oxide-nitride-oxide layer in the peripheral low voltage circuit region;

    conducting a double diffused drain ion implantation process to form a double diffused drain structure in the substrate on both sides of the high voltage gate electrode in the peripheral high voltage circuit region;

    forming a first source/drain region that comprises the double diffused drain structure on both sides of the gate electrode in the substrate, and a second source/drain region on one side of the floating gate in the substrate;

    forming a gate oxide layer on the peripheral low voltage circuit region;

    forming a control gate on the oxide/nitride/oxide layer of the memory device region and low voltage gate electrode on the gate oxide layer of the peripheral low voltage circuit region; and

    forming a third source/drain region on the substrate on both sides of the low voltage gate electrode.

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