Trench gated power device fabrication by doping side walls of partially filled trench

• US 6,274,437 B1
• Filed: 01/27/1998
• Issued: 08/14/2001
• Est. Priority Date: 06/14/1995
• Status: Expired due to Term

• Current Assignee: Totem Semiconductor Limited
• Original Assignee: Totem Semiconductor Limited
• Inventors: Evans, Jonathan Leslie
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): EATON, KURT M
• Application Number:
  US08/973,147
• Time in Patent Office: 1,295 Days
• Field of Search: 438/675, 438/137, 438/138, 438/156, 438/173, 438/192, 438/206, 438/212, 438/268, 438/514, 438/523, 438/524, 438/525, 438/700, 438/FOR.176, 438/FOR.192, 438/272, 438/239, 438/209, 438/315, 438/270, 257/329, 257/330, 257/333
• US Class Current: 438/272
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/0865 Disposition
• CPC Class Codes: H01L 29/0869 Shape cell layout H01L29/0696
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/66613 with a gate recessing step, e.g. using local oxidation making recessed gate LDMOS transistors H01L29/66704
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A trench is formed in a semiconductor substrate using a mask. The trench is filled with electrode material, a part of which is removed; alternatively, the trench is partially filled with the electrode material. The side walls of the trench are doped with the mask still in place. After the side walls are doped, the remainder of the trench is filled. The result is a trench gated power device such as a MOSFET, MESFET or IGBT.

Claims

1. A method of fabricating a trench gated power device, the method comprising:

(i) forming a trench in a semiconductor substrate using a mask to define the trench region;

(ii) either

a) filling the trench with electrode material and removing part of the contents of the trench to leave a partially filled trench;

or

b) partially filling the trench with electrode material;

(iii) doping the side walls of the partially filled trench with the mask still in place; and

(iv) filling the remainder of the trench after step (iii);

wherein the trench gated power device is one selected from the group consisting of a MOSFET, MESFET and IGBT.

2. A method according to claim 1 further comprising forming a layer of dielectric on the surface of the trench between steps (i) and (ii).

3. A method according to claim 2, wherein step (iii) is carried out through the dielectric layer.

4. A method according to claim 2, further comprising removing the layer of dielectric from the exposed part of the trench after step (ii).

5. A method according to claim 1, wherein step (iii) comprises implanting dopant ions from an angled ionic source.

6. A method according to claim 5, wherein the angle of the ionic source to the surface of the substrate is large enough such that ionic reflections from the side walls of the trench causes substantially all sides of the trench to be at least partially doped in one implanting step.

7. A method according to claim 1, wherein step (iii) comprises diffusing dopant ions into the sidewalls of the trench from a dopant gas.

8. A method according to claim 1, wherein step (iii) comprises implanting dopant ions from an isotropic source.

9. A method according to claim 1, wherein step (iv) comprises filling the trench with oxide.

10. A method according to claim 1, wherein:

the semiconductor substrate comprises;

a doped lower layer selected from the group consisting of an n+++ doped

lower layer and a p+++ doped lower layer;

an n−

drain drift region disposed on the doped lower layer; and

a p base region disposed on the n−

drain drift region; and

step (i) comprises forming the trench in the p base region.